Re: [PATCH v2] x86/apic: reduce cache line misses in __x2apic_send_IPI_mask()

[Peter Zijlstra]

On Thu, Oct 07, 2021 at 07:35:56AM -0700, Eric Dumazet wrote:
> From: Eric Dumazet <edumazet@xxxxxxxxxx>
> 
> Using per-cpu storage for @x86_cpu_to_logical_apicid
> is not optimal.
> 
> Broadcast IPI will need at least one cache line
> per cpu to access this field.
> 
> __x2apic_send_IPI_mask() is using standard bitmask operators.
> 
> By converting x86_cpu_to_logical_apicid to an array,
> we divide by 16x number of needed cache lines, because
> we find 16 values per cache line. CPU prefetcher can
> kick nicely.
> 
> Also move @cluster_masks to READ_MOSTLY section to avoid false sharing.
> 
> Tested on a dual socket host with 256 cpus,
> cost for a full broadcast is now 11 usec instead of 33 usec.
> 
> v2: use a dynamically allocated array, as suggested by Peter.
> 
> Signed-off-by: Eric Dumazet <edumazet@xxxxxxxxxx>

Acked-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>