Re: [PATCH 6/8] phy: uniphier-pcie: Add dual-phy support for NX1 SoC
From: kernel test robot
Date: Sun Oct 17 2021 - 23:43:17 EST
Hi Kunihiko,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.15-rc5 next-20211015]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Kunihiko-Hayashi/phy-socionext-Introduce-some-features-for-UniPhier-SoCs/20211018-093816
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: riscv-randconfig-r042-20211018 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project d245f2e8597bfb52c34810a328d42b990e4af1a4)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/0day-ci/linux/commit/a3f73681b86f6da2c6617b1f3baf5d046582d33d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Kunihiko-Hayashi/phy-socionext-Introduce-some-features-for-UniPhier-SoCs/20211018-093816
git checkout a3f73681b86f6da2c6617b1f3baf5d046582d33d
# save the attached .config to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/phy/socionext/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>
All errors (new ones prefixed by >>):
>> drivers/phy/socionext/phy-uniphier-pcie.c:181:48: error: too few arguments to function call, expected 5, have 4
FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL));
^
drivers/phy/socionext/phy-uniphier-pcie.c:95:13: note: 'uniphier_pciephy_set_param' declared here
static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
^
1 error generated.
vim +181 drivers/phy/socionext/phy-uniphier-pcie.c
c6d9b132415951 Kunihiko Hayashi 2018-09-05 140
c6d9b132415951 Kunihiko Hayashi 2018-09-05 141 static int uniphier_pciephy_init(struct phy *phy)
c6d9b132415951 Kunihiko Hayashi 2018-09-05 142 {
c6d9b132415951 Kunihiko Hayashi 2018-09-05 143 struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 144 u32 val;
a3f73681b86f6d Kunihiko Hayashi 2021-10-18 145 int ret, id;
c6d9b132415951 Kunihiko Hayashi 2018-09-05 146
c6d9b132415951 Kunihiko Hayashi 2018-09-05 147 ret = clk_prepare_enable(priv->clk);
c6d9b132415951 Kunihiko Hayashi 2018-09-05 148 if (ret)
c6d9b132415951 Kunihiko Hayashi 2018-09-05 149 return ret;
c6d9b132415951 Kunihiko Hayashi 2018-09-05 150
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 151 ret = clk_prepare_enable(priv->clk_gio);
c6d9b132415951 Kunihiko Hayashi 2018-09-05 152 if (ret)
c6d9b132415951 Kunihiko Hayashi 2018-09-05 153 goto out_clk_disable;
c6d9b132415951 Kunihiko Hayashi 2018-09-05 154
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 155 ret = reset_control_deassert(priv->rst);
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 156 if (ret)
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 157 goto out_clk_gio_disable;
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 158
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 159 ret = reset_control_deassert(priv->rst_gio);
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 160 if (ret)
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 161 goto out_rst_assert;
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 162
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 163 /* support only 1 port */
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 164 val = readl(priv->base + PCL_PHY_CLKCTRL);
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 165 val &= ~PORT_SEL_MASK;
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 166 val |= PORT_SEL_1;
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 167 writel(val, priv->base + PCL_PHY_CLKCTRL);
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 168
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 169 /* legacy controller doesn't have phy_reset and parameters */
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 170 if (priv->data->is_legacy)
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 171 return 0;
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 172
a3f73681b86f6d Kunihiko Hayashi 2021-10-18 173 for (id = 0; id < (priv->data->is_dual_phy ? 2 : 1); id++) {
a3f73681b86f6d Kunihiko Hayashi 2021-10-18 174 uniphier_pciephy_set_param(priv, id, PCL_PHY_R00,
c6d9b132415951 Kunihiko Hayashi 2018-09-05 175 RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
a3f73681b86f6d Kunihiko Hayashi 2021-10-18 176 uniphier_pciephy_set_param(priv, id, PCL_PHY_R06, RX_EQ_ADJ,
c6d9b132415951 Kunihiko Hayashi 2018-09-05 177 FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
a3f73681b86f6d Kunihiko Hayashi 2021-10-18 178 uniphier_pciephy_set_param(priv, id, PCL_PHY_R26, VCO_CTRL,
c6d9b132415951 Kunihiko Hayashi 2018-09-05 179 FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
27db30df224a79 Kunihiko Hayashi 2021-10-18 180 uniphier_pciephy_set_param(priv, PCL_PHY_R28, VCOPLL_CLMP,
27db30df224a79 Kunihiko Hayashi 2021-10-18 @181 FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL));
a3f73681b86f6d Kunihiko Hayashi 2021-10-18 182 }
c6d9b132415951 Kunihiko Hayashi 2018-09-05 183 usleep_range(1, 10);
c6d9b132415951 Kunihiko Hayashi 2018-09-05 184
c6d9b132415951 Kunihiko Hayashi 2018-09-05 185 uniphier_pciephy_deassert(priv);
c6d9b132415951 Kunihiko Hayashi 2018-09-05 186 usleep_range(1, 10);
c6d9b132415951 Kunihiko Hayashi 2018-09-05 187
c6d9b132415951 Kunihiko Hayashi 2018-09-05 188 return 0;
c6d9b132415951 Kunihiko Hayashi 2018-09-05 189
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 190 out_rst_assert:
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 191 reset_control_assert(priv->rst);
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 192 out_clk_gio_disable:
04de8fa202e6d5 Kunihiko Hayashi 2020-01-30 193 clk_disable_unprepare(priv->clk_gio);
c6d9b132415951 Kunihiko Hayashi 2018-09-05 194 out_clk_disable:
c6d9b132415951 Kunihiko Hayashi 2018-09-05 195 clk_disable_unprepare(priv->clk);
c6d9b132415951 Kunihiko Hayashi 2018-09-05 196
c6d9b132415951 Kunihiko Hayashi 2018-09-05 197 return ret;
c6d9b132415951 Kunihiko Hayashi 2018-09-05 198 }
c6d9b132415951 Kunihiko Hayashi 2018-09-05 199
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
Attachment:
.config.gz
Description: application/gzip