Re: [PATCH v2 1/2] riscv: consolidate __ex_table construction

[Jisheng Zhang]

On Thu, 21 Oct 2021 19:38:41 +0800
Kefeng Wang <wangkefeng.wang@xxxxxxxxxx> wrote:

> On 2021/10/20 22:06, Jisheng Zhang wrote:
> > From: Jisheng Zhang <jszhang@xxxxxxxxxx>
> > 
> > Consolidate all the __ex_table constuction code with a _ASM_EXTABLE
> > helper.
> > 
> > There should be no functional change as a result of this patch.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
> > ---
> >   arch/riscv/include/asm/futex.h   | 12 +++-------
> >   arch/riscv/include/asm/uaccess.h | 40 +++++++++++---------------------
> >   2 files changed, 17 insertions(+), 35 deletions(-)
> > 
> > diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h
> > index 1b00badb9f87..3191574e135c 100644
> > --- a/arch/riscv/include/asm/futex.h
> > +++ b/arch/riscv/include/asm/futex.h
> > @@ -30,10 +30,7 @@
> >   	"3:	li %[r],%[e]				\n"	\
> >   	"	jump 2b,%[t]				\n"	\
> >   	"	.previous				\n"	\
> > -	"	.section __ex_table,\"a\"		\n"	\
> > -	"	.balign " RISCV_SZPTR "			\n"	\
> > -	"	" RISCV_PTR " 1b, 3b			\n"	\
> > -	"	.previous				\n"	\
> > +		_ASM_EXTABLE(1b, 3b)				\
> >   	: [r] "+r" (ret), [ov] "=&r" (oldval),			\
> >   	  [u] "+m" (*uaddr), [t] "=&r" (tmp)			\
> >   	: [op] "Jr" (oparg), [e] "i" (-EFAULT)			\
> > @@ -103,11 +100,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
> >   	"4:	li %[r],%[e]				\n"
> >   	"	jump 3b,%[t]				\n"
> >   	"	.previous				\n"
> > -	"	.section __ex_table,\"a\"		\n"
> > -	"	.balign " RISCV_SZPTR "			\n"
> > -	"	" RISCV_PTR " 1b, 4b			\n"
> > -	"	" RISCV_PTR " 2b, 4b			\n"
> > -	"	.previous				\n"
> > +		_ASM_EXTABLE(1b, 4b)			\
> > +		_ASM_EXTABLE(2b, 4b)			\
> >   	: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp)
> >   	: [ov] "Jr" (oldval), [nv] "Jr" (newval), [e] "i" (-EFAULT)
> >   	: "memory");
> > diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h
> > index f314ff44c48d..35802e72ace8 100644
> > --- a/arch/riscv/include/asm/uaccess.h
> > +++ b/arch/riscv/include/asm/uaccess.h
> > @@ -10,6 +10,12 @@
> >   
> >   #include <asm/pgtable.h>		/* for TASK_SIZE */
> >   
> > +#define _ASM_EXTABLE(from, to)						\
> > +	"	.pushsection	__ex_table, \"a\"\n"			\
> > +	"	.balign "	RISCV_SZPTR "	 \n"			\
> > +	"	" RISCV_PTR	"(" #from "), (" #to ")\n"		\
> > +	"	.popsection\n"
> > +  
> 
> The jump_label mechanism could use this macro too,
> see arch/riscv/include/asm/jump_label.h, maybe move the above into asm.h
> and also do some replace in next patch ?

jump_label entry is a bit different with ex_table: two relative offsets and
a key which should be "long" type.

> 
> Question: the jump label use relative address, but why not trigger the 
> Section mismatch issue?

FWICT, modpost doesn't check __jump_table section