[tip: timers/core] Merge branch 'timers/drivers/armv8.6_arch_timer' into timers/drivers/next

[tip-bot2 for Daniel Lezcano]

The following commit has been merged into the timers/core branch of tip:

Commit-ID:     32cf6d0ae0d86a31aa21b5d8ce6820486027c254
Gitweb:        https://git.kernel.org/tip/32cf6d0ae0d86a31aa21b5d8ce6820486027c254
Author:        Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
AuthorDate:    Tue, 19 Oct 2021 10:07:28 +02:00
Committer:     Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
CommitterDate: Tue, 19 Oct 2021 10:07:28 +02:00

Merge branch 'timers/drivers/armv8.6_arch_timer' into timers/drivers/next

The branch is a stable branch shared with ARM maintainers for the
first 13th patches of the series:

It is based on v5.14-rc3.

As stated by the changelog:

" [... ] enabling ARMv8.6 support for timer subsystem, and was prompted by a
discussion with Oliver around the fact that an ARMv8.6 implementation
must have a 1GHz counter, which leads to a number of things to break
in the timer code:

- the counter rollover can come pretty quickly as we only advertise a
  56bit counter,
- the maximum timer delta can be remarkably small, as we use the
  countdown interface which is limited to 32bit...

Thankfully, there is a way out: we can compute the minimal width of
the counter based on the guarantees that the architecture gives us,
and we can use the 64bit comparator interface instead of the countdown
to program the timer.

Finally, we start making use of the ARMv8.6 ECV features by switching
accesses to the counters to a self-synchronising register, removing
the need for an ISB. Hopefully, implementations will *not* just stick
an invisible ISB there...

A side effect of the switch to CVAL is that XGene-1 breaks. I have
added a workaround to keep it alive.

I have added Oliver's original patch[0] to the series and tweaked a
couple of things. Blame me if I broke anything.

The whole things has been tested on Juno (sysreg + MMIO timers),
XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0).
"

Link: https://lore.kernel.org/r/20211017124225.3018098-1-maz@xxxxxxxxxx
Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
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