On 25-10-21, 17:40, Dmitry Baryshkov wrote:
On 20/10/2021 09:57, Vinod Koul wrote:
On 14-10-21, 16:50, Dmitry Baryshkov wrote:
On 14/10/2021 16:41, Dmitry Baryshkov wrote:
On 07/10/2021 10:08, Vinod Koul wrote:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 806c171e5df2..5dfac5994bd4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg {
* @mode_3d: 3d mux configuration
* @merge_3d: 3d merge block used
* @intf_mode_sel: Interface mode, cmd / vid
+ * @dsc: DSC BIT masks
* @stream_sel: Stream selection for multi-stream interfaces
*/
struct dpu_hw_intf_cfg {
@@ -46,6 +47,7 @@ struct dpu_hw_intf_cfg {
enum dpu_3d_blend_mode mode_3d;
enum dpu_merge_3d merge_3d;
enum dpu_ctl_mode_sel intf_mode_sel;
+ unsigned int dsc;
I think this should be:
enum dpu_dsc dsc[MAX_DSCS];
unsigned int num_dsc;
hmmm, how do we go about getting the num_dsc value here.
dpu_encoder_phys does not know about that..
dpu_encoder_get_topology() can decide whether to use DSC or not and then set
num_dsc. For now it will always set 2 if we are using DSC at all, but let's
keep the decision in a single place rather than having it scattered all over
the driver.
Yes agree, but dpu_encoder_get_topology() is private to encoder. Am not
sure how best to propagate the info into the hw_intf_cfg?