RE: [PATCH v4 7/8] arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board

[Richard Zhu]

> -----Original Message-----
> From: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
> Sent: Friday, October 29, 2021 4:21 PM
> To: kishon@xxxxxx; vkoul@xxxxxxxxxx; robh@xxxxxxxxxx;
> l.stach@xxxxxxxxxxxxxx; shawnguo@xxxxxxxxxx;
> tharvey@xxxxxxxxxxxxx; galak@xxxxxxxxxxxxxxxxxxx; Richard Zhu
> <hongxing.zhu@xxxxxxx>
> Cc: linux-phy@xxxxxxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>
> Subject: Re: [PATCH v4 7/8] arm64: dts: imx8mm-evk: Add the pcie
> support on imx8mm evk board
> 
> On Thu, 2021-10-28 at 15:27 +0800, Richard Zhu wrote:
> > Add the PCIe support on iMX8MM EVK boards.
> > And set the default reference clock mode.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > Tested-by: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 55
> > +++++++++++++++++++
> >  1 file changed, 55 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > index e033d0257b5a..fc1803a8af5b 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > @@ -5,6 +5,7 @@
> >
> >  /dts-v1/;
> >
> > +#include <dt-bindings/phy/phy-imx8-pcie.h>
> >  #include <dt-bindings/usb/pd.h>
> >  #include "imx8mm.dtsi"
> >
> > @@ -30,6 +31,23 @@ status {
> >                 };
> >         };
> >
> > +       pcie0_refclk: pcie0-refclk {
> > +               compatible = "fixed-clock";
> > +                       #clock-cells = <0>;
> > +                       clock-frequency = <100000000>;
> > +       };
> > +
> > +       reg_pcie0: regulator-pcie {
> > +               compatible = "regulator-fixed";
> > +               pinctrl-names = "default";
> > +               pinctrl-0 = <&pinctrl_pcie0_reg>;
> > +               regulator-name = "MPCIE_3V3";
> > +               regulator-min-microvolt = <3300000>;
> > +               regulator-max-microvolt = <3300000>;
> > +               gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
> > +               enable-active-high;
> > +       };
> > +
> >         reg_usdhc2_vmmc: regulator-usdhc2 {
> >                 compatible = "regulator-fixed";
> >                 pinctrl-names = "default"; @@ -289,6 +307,30
> @@
> > pca6416: gpio@20 {
> >         };
> >  };
> >
> > +&pcie_phy {
> > +       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> > +       fsl,tx-deemph-gen1 = <0x2D>;
> > +       fsl,tx-deemph-gen2 = <0xF>;
> 
> Usually, hex notation uses lower-case letters in device trees.
[Richard Zhu] Okay, would be changed later in next version later.
Thanks

BR
Richard
> 
> > +       clocks = <&pcie0_refclk>;
> > +       status = "okay";
> > +};
> > +
> > +&pcie0 {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_pcie0>;
> > +       reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> > +       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> > +IMX8MM_CLK_PCIE1_AUX>,
> > +                <&pcie0_refclk>;
> > +       clock-names = "pcie", "pcie_aux", "pcie_bus";
> > +       assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> > +                         <&clk
> IMX8MM_CLK_PCIE1_CTRL>;
> > +       assigned-clock-rates = <10000000>, <250000000>;
> > +       assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
> > +                                <&clk
> IMX8MM_SYS_PLL2_250M>;
> > +       vpcie-supply = <&reg_pcie0>;
> > +       status = "okay";
> > +};
> > +
> >  &sai3 {
> >         pinctrl-names = "default";
> >         pinctrl-0 = <&pinctrl_sai3>;
> > @@ -406,6 +448,19 @@
> MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA
> > 0x400001c3
> >                 >;
> >         };
> >
> > +       pinctrl_pcie0: pcie0grp {
> > +               fsl,pins = <
> >
> +                       MX8MM_IOMUXC_I2C4_SCL_PCIE1
> _CLKREQ_B    0x61
> >
> +                       MX8MM_IOMUXC_SAI2_RXFS_GPIO
> 4_IO21       0x41
> > +               >;
> > +       };
> > +
> > +       pinctrl_pcie0_reg: pcie0reggrp {
> > +               fsl,pins = <
> >
> +                       MX8MM_IOMUXC_GPIO1_IO05_GPI
> O1_IO5       0x41
> > +               >;
> > +       };
> > +
> >         pinctrl_pmic: pmicirqgrp {
> >                 fsl,pins = <
> >                         MX8MM_IOMUXC_GPIO1_IO03_
> GPIO1_IO3
> > 0x141