Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT

[Marc Zyngier]

On Mon, 01 Nov 2021 02:20:21 +0000,
Guo Ren <guoren@xxxxxxxxxx> wrote:
> 
> On Thu, Oct 28, 2021 at 10:58 PM Marc Zyngier <maz@xxxxxxxxxx> wrote:
> >
> > On Thu, 28 Oct 2021 11:55:23 +0100,
> > Nikita Shubin <nikita.shubin@xxxxxxxxxxx> wrote:
> > >
> > > Hello Marc and Guo Ren!
> > >
> > > On Mon, 25 Oct 2021 11:48:33 +0100
> > > Marc Zyngier <maz@xxxxxxxxxx> wrote:
> > >
> > > > On Sun, 24 Oct 2021 02:33:03 +0100,
> > > > guoren@xxxxxxxxxx wrote:
> > > > >
> > > > > From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
> > > > >
> > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the
> > > > > driver, only the first interrupt could be handled, and continue irq
> > > > > is blocked by hw. Because the thead,c900-plic couldn't complete
> > > > > masked irq source which has been disabled in enable register. Add
> > > > > thead_plic_chip which fix up c906-plic irq source completion
> > > > > problem by unmask/mask wrapper.
> > > > >
> > > > > Here is the description of Interrupt Completion in PLIC spec [1]:
> > > > >
> > > > > The PLIC signals it has completed executing an interrupt handler by
> > > > > writing the interrupt ID it received from the claim to the
> > > > > claim/complete register. The PLIC does not check whether the
> > > > > completion ID is the same as the last claim ID for that target. If
> > > > > the completion ID does not match an interrupt source that is
> > > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^
> > > > > completion is silently ignored.
> > > >
> > > > Given this bit of the spec...
> > > >
> > > > > +static void plic_thead_irq_eoi(struct irq_data *d)
> > > > > +{
> > > > > + struct plic_handler *handler =
> > > > > this_cpu_ptr(&plic_handlers); +
> > > > > + if (irqd_irq_masked(d)) {
> > > > > +         plic_irq_unmask(d);
> > > > > +         writel(d->hwirq, handler->hart_base +
> > > > > CONTEXT_CLAIM);
> > > > > +         plic_irq_mask(d);
> > > > > + } else {
> > > > > +         writel(d->hwirq, handler->hart_base +
> > > > > CONTEXT_CLAIM);
> > > > > + }
> > > > > +}
> > > > > +
> > > >
> > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC.
> > >
> > > This indeed happens with SiFive PLIC. I am currently tinkering with
> > > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However
> > > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything
> > > begins to work fine.
> > >
> > > May be these change should be propagated to plic_irq_eoi instead of
> > > making a new function ?
> >
> > That's my impression too. I think the T-Head defect is pretty much
> > immaterial when you consider how 'interesting' the PLIC architecture
> > is.
> Which is the "T-Head defect" you mentioned here?
>  1. Auto masking with claim + complete (I don't think it's a defect,
> right? May I add a new patch to utilize the feature to decrease a
> little duplicate mask/unmask operations in the future?)

That *is* a T-Head defect. It may not be material for Linux, but being
a departure from the spec, it is a bug, clear and simple. IMHO, either
you implement the spec to the letter, or you don't. If you deviate,
this is something else.

>  2. EOI failed when masked

This one is a PLIC architecture defect, which seems to plague everyone.

> 
> > Conflating EOI and masking really is a misfeature...
> I think the problem is riscv PLIC reuse enable bit as mask bit. I
> recommend separating them. That means:
>  - EOI still depends on enable bit.
>  - Add mask/unmask bit regs to do the right thing.

Maybe, but that's not the problem at hand. I suggest you move
architectural discussions to a separate thread, and keep this thread
for fixing the mess that plagues existing users.

	M.

-- 
Without deviation from the norm, progress is not possible.