On Tue, Nov 02, 2021 at 07:19:46PM +0200, Grygorii Strashko wrote:
It would require MDIO bus lock, which is not a solution,
or some sort of batch processing, like for mmd:
w reg1 val1
w reg2 val2
w reg1 val3
r reg2
What Kernel interface do you have in mind?
That is roughly what I was thinking, but Andrew has basically said no
to it.
Sry, but I have to note that demand for this become terribly high, min two pings in months
Feel free to continue demanding it, but it seems that at least two of
the phylib maintainers are in agreement that providing generic
emulation of C45 accesses in kernel space is just not going to happen.