Re: [PATCH v3 01/21] x86/cpufreatures: add AMD Collaborative Processor Performance Control feature flag

[Huang Rui]

On Sat, Nov 06, 2021 at 06:28:54PM +0800, Borislav Petkov wrote:
> On Fri, Oct 29, 2021 at 09:02:21PM +0800, Huang Rui wrote:
> > Add Collaborative Processor Performance Control feature flag for AMD
> > processors.
> > 
> > This feature flag will be used on the following amd-pstate driver. The
> > amd-pstate driver has two approaches to implement the frequency control
> > behavior. That depends on the CPU hardware implementation. One is "Full
> > MSR Support" and another is "Shared Memory Support". The feature flag
> > indicates the current processors with "Full MSR Support".
> > 
> > Signed-off-by: Huang Rui <ray.huang@xxxxxxx>
> > ---
> >  arch/x86/include/asm/cpufeatures.h | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index d0ce5cfd3ac1..f23dc1abd485 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -313,6 +313,7 @@
> >  #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
> >  #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
> >  #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
> > +#define X86_FEATURE_AMD_CPPC		(13*32+27) /* Collaborative Processor Performance Control */
> 
> I know I have acked this already but an Intel patchset made me look at
> this again: there's no need to have the vendor name in the feature name:
> 
> X86_FEATURE_CPPC
> 
> is perfectly fine.
> 

Fine. Will update it in V4.

Thanks,
Ray