drivers/gpu/drm/msm/adreno/a6xx_gpu.c:1643:6: sparse: sparse: symbol 'a6xx_gpu_set_freq' was not declared. Should it be static?

From: kernel test robot
Date: Wed Nov 17 2021 - 07:19:57 EST

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Hi Stephen,

First bad commit (maybe
tree: config: alpha-randconfig-s031-20211117 compiler: alpha-linux-gcc reproduce:
wget # apt-get install sparse
# sparse version: # If you fix the issue, Reported-by: kernel

sparse warnings: (new drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno >> drivers/gpu/drm/m drivers/gpu/drm/msm/adreno/a6xx_gpu.c: drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno drivers/gpu/drm/msm/adreno
vim +/a6xx_gpu_set_freq
474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 3d247123b5a16f5 Jordan Crouse 4b95d371fb00118 Jonathan Marek 4b95d371fb00118 Jonathan Marek 4b95d371fb00118 Jonathan Marek 4b95d371fb00118 Jonathan Marek 4b95d371fb00118 Jonathan Marek 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 276619c0923f8fa Sai 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse ec1cb6e4408abe5 Rob Clark ec1cb6e4408abe5 Rob Clark f6f59072e821901 Rob Clark 41570b747cf3ae8 Jordan Crouse f6f59072e821901 Rob Clark 41570b747cf3ae8 Jordan Crouse 41570b747cf3ae8 Jordan Crouse 41570b747cf3ae8 Jordan Crouse af5b4fff0fe80c8 Rob Clark a2c3c0a54d4cccb Sharat Masetty 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 41570b747cf3ae8 Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse e8b0b994c3a5881 Rob Clark 4b565ca5a2cbbbb Jordan Crouse ec1cb6e4408abe5 Rob Clark ec1cb6e4408abe5 Rob Clark 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty af5b4fff0fe80c8 Rob Clark a2c3c0a54d4cccb Sharat Masetty f6f59072e821901 Rob Clark e8b0b994c3a5881 Rob Clark f6f59072e821901 Rob Clark e8b0b994c3a5881 Rob Clark e8b0b994c3a5881 Rob Clark e8b0b994c3a5881 Rob Clark ce86c239e4d218a Jonathan Marek e8b0b994c3a5881 Rob Clark e8b0b994c3a5881 Rob Clark e8b0b994c3a5881 Rob Clark e8b0b994c3a5881 Rob Clark 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 5f98b33b04c02c0 Eric Anholt f6f59072e821901 Rob Clark 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 7a7cbf2a8197406 Eric Anholt 4b565ca5a2cbbbb Jordan Crouse 9fbd3088351b92e Rob Clark 9fbd3088351b92e Rob Clark 4b565ca5a2cbbbb Jordan Crouse 7a7cbf2a8197406 Eric Anholt f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 7ad0e8cf6317825 Jordan Crouse f7d33950cd6a70a Emil Velikov 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse d3a569fccfa087a Jordan Crouse d3a569fccfa087a Jordan Crouse d3a569fccfa087a Jordan Crouse d3a569fccfa087a Jordan Crouse d3a569fccfa087a Jordan Crouse 474dadb8b0d5576 Sharat Masetty 474dadb8b0d5576 Sharat Masetty 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse fe7952c629daec6 Akhil P Oommen 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse 4b565ca5a2cbbbb Jordan Crouse a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty 16f37102181e23e Sean Paul a2c3c0a54d4cccb Sharat Masetty eadf79286a4bade Jordan Crouse eadf79286a4bade Jordan Crouse eadf79286a4bade Jordan Crouse eadf79286a4bade Jordan Crouse eadf79286a4bade Jordan Crouse a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty 16f37102181e23e Sean Paul 16f37102181e23e Sean Paul a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty eadf79286a4bade Jordan Crouse eadf79286a4bade Jordan Crouse 16f37102181e23e Sean Paul 16f37102181e23e Sean Paul 16f37102181e23e Sean Paul 16f37102181e23e Sean Paul a2c3c0a54d4cccb Sharat Masetty a2c3c0a54d4cccb Sharat Masetty f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark f6f59072e821901 Rob Clark
:::::: The code at line :::::: f6f59072e821901d96c791
:::::: TO: Rob Clark :::::: CC: Rob Clark
---
0-DAY CI Kernel Test Description: application/gzip Konrad Dybcio: "Re: [PATCH 1/2] dt-bindings: soc: qcom: llcc-qcom: Add SM8350 compatible and defines" message: Guo Zhengkui: "[PATCH] video: omapfb: Use scnprintf() instead of snprintf()" sorted by: [ date ] [ thread ] [ subject ] [ author ] != root cause):
href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
471cc723bba6d893942
dd0757b18871cc983ab BackMerge tag 'v5.15-rc7' into drm-next
(attached as .config)
(GCC) 11.2.0
href="https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross">https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
v0.6.4-dirty
href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=970eae15600a883e4ad27dd0757b18871cc983ab">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=970eae15600a883e4ad27dd0757b18871cc983ab
rel="nofollow" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
linus master
970eae15600a883e4ad27dd0757b18871cc983ab
.config to linux build tree
COMPILER=gcc-11.2.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=alpha SHELL=/bin/bash drivers/gpu/drm/msm/
kindly add following tag as appropriate
test robot <lkp@xxxxxxxxx>
ones prefixed by >>)
/a6xx_gpu.c:1512:36: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void [noderef] __iomem *llc_mmio @@ got void * @@
/a6xx_gpu.c:1512:36: sparse: expected void [noderef] __iomem *llc_mmio
/a6xx_gpu.c:1512:36: sparse: got void *
sm/adreno/a6xx_gpu.c:1643:6: sparse: sparse: symbol 'a6xx_gpu_set_freq' was not declared. Should it be static?
note: in included file (through drivers/gpu/drm/msm/adreno/a6xx_gpu.h):
/a6xx_gmu.h:96:36: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:96:36: sparse: expected void const [noderef] __iomem *addr
/a6xx_gmu.h:96:36: sparse: got void *
/a6xx_gmu.h:96:26: sparse: sparse: dereference of noderef expression
/a6xx_gmu.h:101:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:101:44: sparse: expected void [noderef] __iomem *addr
/a6xx_gmu.h:101:44: sparse: got void *
/a6xx_gmu.h:101:34: sparse: sparse: dereference of noderef expression
/a6xx_gmu.h:96:36: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:96:36: sparse: expected void const [noderef] __iomem *addr
/a6xx_gmu.h:96:36: sparse: got void *
/a6xx_gmu.h:96:26: sparse: sparse: dereference of noderef expression
/a6xx_gmu.h:101:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:101:44: sparse: expected void [noderef] __iomem *addr
/a6xx_gmu.h:101:44: sparse: got void *
/a6xx_gmu.h:101:34: sparse: sparse: dereference of noderef expression
/a6xx_gmu.h:101:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:101:44: sparse: expected void [noderef] __iomem *addr
/a6xx_gmu.h:101:44: sparse: got void *
/a6xx_gmu.h:101:34: sparse: sparse: dereference of noderef expression
/a6xx_gmu.h:101:44: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:101:44: sparse: expected void [noderef] __iomem *addr
/a6xx_gmu.h:101:44: sparse: got void *
/a6xx_gmu.h:101:34: sparse: sparse: dereference of noderef expression
/a6xx_gmu.h:124:41: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:124:41: sparse: expected void const [noderef] __iomem *addr
/a6xx_gmu.h:124:41: sparse: got void *
/a6xx_gmu.h:125:43: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const [noderef] __iomem *addr @@ got void * @@
/a6xx_gmu.h:125:43: sparse: expected void const [noderef] __iomem *addr
/a6xx_gmu.h:125:43: sparse: got void *
/a6xx_gmu.h:124:31: sparse: sparse: dereference of noderef expression
/a6xx_gmu.h:125:33: sparse: sparse: dereference of noderef expression
+1643 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
2020-11-25 1488
2020-11-25 1489 static void a6xx_llc_slices_init(struct platform_device *pdev,
2020-11-25 1490 struct a6xx_gpu *a6xx_gpu)
2020-11-25 1491 {
2020-11-25 1492 struct device_node *phandle;
2020-11-25 1493
2020-11-25 1494 /*
2020-11-25 1495 * There is a different programming path for targets with an mmu500
2020-11-25 1496 * attached, so detect if that is the case
2020-11-25 1497 */
2020-11-25 1498 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
2020-11-25 1499 a6xx_gpu->have_mmu500 = (phandle &&
2020-11-25 1500 of_device_is_compatible(phandle, "arm,mmu-500"));
2020-11-25 1501 of_node_put(phandle);
2020-11-25 1502
2021-04-23 1503 if (a6xx_gpu->have_mmu500)
2021-04-23 1504 a6xx_gpu->llc_mmio = NULL;
2021-04-23 1505 else
2021-04-23 1506 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
2021-04-23 1507
2020-11-25 1508 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
2020-11-25 1509 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
2020-11-25 1510
Prakash Ranjan 2021-01-11 1511 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
2020-11-25 @1512 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
2020-11-25 1513 }
2020-11-25 1514
2018-08-06 1515 static int a6xx_pm_resume(struct msm_gpu *gpu)
2018-08-06 1516 {
2018-08-06 1517 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2018-08-06 1518 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2018-08-06 1519 int ret;
2018-08-06 1520
2018-08-06 1521 gpu->needs_hw_init = true;
2018-08-06 1522
2020-09-01 1523 trace_msm_gpu_resume(0);
2020-09-01 1524
2021-09-27 1525 mutex_lock(&a6xx_gpu->gmu.lock);
2019-02-04 1526 ret = a6xx_gmu_resume(a6xx_gpu);
2021-09-27 1527 mutex_unlock(&a6xx_gpu->gmu.lock);
2019-02-04 1528 if (ret)
2019-02-04 1529 return ret;
2019-02-04 1530
2021-07-26 1531 msm_devfreq_resume(gpu);
2018-10-04 1532
2020-11-25 1533 a6xx_llc_activate(a6xx_gpu);
2020-11-25 1534
2019-02-04 1535 return 0;
2018-08-06 1536 }
2018-08-06 1537
2018-08-06 1538 static int a6xx_pm_suspend(struct msm_gpu *gpu)
2018-08-06 1539 {
2018-08-06 1540 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2018-08-06 1541 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2020-11-10 1542 int i, ret;
2018-08-06 1543
2020-09-01 1544 trace_msm_gpu_suspend(0);
2020-09-01 1545
2020-11-25 1546 a6xx_llc_deactivate(a6xx_gpu);
2020-11-25 1547
2021-07-26 1548 msm_devfreq_suspend(gpu);
2018-10-04 1549
2021-09-27 1550 mutex_lock(&a6xx_gpu->gmu.lock);
2020-11-10 1551 ret = a6xx_gmu_stop(a6xx_gpu);
2021-09-27 1552 mutex_unlock(&a6xx_gpu->gmu.lock);
2020-11-10 1553 if (ret)
2020-11-10 1554 return ret;
2020-11-10 1555
2021-05-13 1556 if (a6xx_gpu->shadow_bo)
2020-11-10 1557 for (i = 0; i < gpu->nr_rings; i++)
2020-11-10 1558 a6xx_gpu->shadow[i] = 0;
2020-11-10 1559
2020-11-10 1560 return 0;
2018-08-06 1561 }
2018-08-06 1562
2018-08-06 1563 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
2018-08-06 1564 {
2018-08-06 1565 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2018-08-06 1566 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2021-01-28 1567
2021-09-27 1568 mutex_lock(&a6xx_gpu->gmu.lock);
2018-08-06 1569
2018-08-06 1570 /* Force the GPU power on so we can read this register */
2021-01-28 1571 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
2018-08-06 1572
2021-03-24 1573 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
2021-03-24 1574 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
2018-08-06 1575
2021-01-28 1576 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
2021-09-27 1577
2021-09-27 1578 mutex_unlock(&a6xx_gpu->gmu.lock);
2021-09-27 1579
2018-08-06 1580 return 0;
2018-08-06 1581 }
2018-08-06 1582
2018-08-06 1583 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
2018-08-06 1584 {
2018-08-06 1585 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2018-08-06 1586 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2018-08-06 1587
2018-08-06 1588 return a6xx_gpu->cur_ring;
2018-08-06 1589 }
2018-08-06 1590
2018-08-06 1591 static void a6xx_destroy(struct msm_gpu *gpu)
2018-08-06 1592 {
2018-08-06 1593 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2018-08-06 1594 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2018-08-06 1595
2018-08-06 1596 if (a6xx_gpu->sqe_bo) {
2018-11-07 1597 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
2020-05-15 1598 drm_gem_object_put(a6xx_gpu->sqe_bo);
2018-08-06 1599 }
2018-08-06 1600
2020-09-14 1601 if (a6xx_gpu->shadow_bo) {
2020-09-14 1602 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
2020-09-14 1603 drm_gem_object_put(a6xx_gpu->shadow_bo);
2020-09-14 1604 }
2020-09-14 1605
2020-11-25 1606 a6xx_llc_slices_destroy(a6xx_gpu);
2020-11-25 1607
2018-08-06 1608 a6xx_gmu_remove(a6xx_gpu);
2018-08-06 1609
2018-08-06 1610 adreno_gpu_cleanup(adreno_gpu);
2021-01-08 1611
2018-08-06 1612 kfree(a6xx_gpu);
2018-08-06 1613 }
2018-08-06 1614
2018-10-04 1615 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
2018-10-04 1616 {
2018-10-04 1617 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2018-10-04 1618 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2018-10-08 1619 u64 busy_cycles, busy_time;
2018-10-04 1620
2020-05-01 1621
2020-05-01 1622 /* Only read the gpu busy if the hardware is already active */
2020-05-01 1623 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
2020-05-01 1624 return 0;
2020-05-01 1625
2018-10-04 1626 busy_cycles = gmu_read64(&a6xx_gpu->gmu,
2018-10-04 1627 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
2018-10-04 1628 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
2018-10-04 1629
2018-10-08 1630 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
2018-10-08 1631 do_div(busy_time, 192);
2018-10-04 1632
2018-10-04 1633 gpu->devfreq.busy_cycles = busy_cycles;
2018-10-04 1634
2020-05-01 1635 pm_runtime_put(a6xx_gpu->gmu.dev);
2020-05-01 1636
2018-10-08 1637 if (WARN_ON(busy_time > ~0LU))
2018-10-08 1638 return ~0LU;
2018-10-08 1639
2018-10-08 1640 return (unsigned long)busy_time;
2018-10-04 1641 }
2018-10-04 1642
2021-09-27 @1643 void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
2021-09-27 1644 {
2021-09-27 1645 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2021-09-27 1646 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2021-09-27 1647
2021-09-27 1648 mutex_lock(&a6xx_gpu->gmu.lock);
2021-09-27 1649 a6xx_gmu_set_freq(gpu, opp);
2021-09-27 1650 mutex_unlock(&a6xx_gpu->gmu.lock);
2021-09-27 1651 }
2021-09-27 1652
1643 was first introduced by commit
864a07d57d8ec8d312 drm/msm/a6xx: Serialize GMU communication
<robdclark@xxxxxxxxxxxx>
<robdclark@xxxxxxxxxxxx>
Service, Intel Corporation
s://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx">https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
>.config.gz

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