Re: [PATCH] PCI: apple: Reset the port for 100ms on probe
From: Marc Zyngier
Date: Thu Nov 18 2021 - 05:45:24 EST
On Thu, 18 Nov 2021 10:01:58 +0000,
Marc Zyngier <maz@xxxxxxxxxx> wrote:
> There is also a third delay (Tperst-clk) which represents the time
> required for the clock to ramp up before releasing #PERST. No, there
> is no value associated with this.
Actually, there is. At least the PCIe CMS r2.0 (2.6.2. AC
Specifications) does provide a table of the timings. Tperst-clk has a
minimum value of 100us.
Which means I can tighten things further.
Without deviation from the norm, progress is not possible.