Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register

From: Paolo Bonzini
Date: Thu Nov 18 2021 - 08:24:06 EST

On 11/18/21 14:03, Like Xu wrote:

This is because according to APM (Revision: 4.03) Figure 13-7,
the bits [35:32] of AMD PerfEvtSeln register is a part of the
event select encoding, which extends the EVENT_SELECT field
from 8 bits to 12 bits.

Queued, thanks.