Re: [PATCH 04/15] KVM: VMX: Add and use X86_CR4_TLB_BITS when !enable_ept

[Paolo Bonzini]

On 11/8/21 13:43, Lai Jiangshan wrote:
> From: Lai Jiangshan <laijs@xxxxxxxxxxxxxxxxx>
>
> In set_cr4_guest_host_mask(), X86_CR4_PGE is set to be intercepted when
> !enable_ept just because X86_CR4_PGE is the only bit that is
> responsible for flushing TLB but listed in KVM_POSSIBLE_CR4_GUEST_BITS.
>
> It is clearer and self-documented to use X86_CR4_TLB_BITS instead.

Very good idea, but I'd go with a slightly clearer X86_CR4_TLBFLUSH_BITS.

Paolo

> No functionality changed.
>
> Signed-off-by: Lai Jiangshan <laijs@xxxxxxxxxxxxxxxxx>
> ---
>   arch/x86/kvm/kvm_cache_regs.h | 2 ++
>   arch/x86/kvm/vmx/vmx.c        | 2 +-
>   2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h
> index 90e1ffdc05b7..8fe036efa654 100644
> --- a/arch/x86/kvm/kvm_cache_regs.h
> +++ b/arch/x86/kvm/kvm_cache_regs.h
> @@ -9,6 +9,8 @@
>   	(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR  \
>   	 | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE)
>   
> +#define X86_CR4_TLB_BITS (X86_CR4_PGE | X86_CR4_PCIDE | X86_CR4_PAE | X86_CR4_SMEP)
> +
>   #define BUILD_KVM_GPR_ACCESSORS(lname, uname)				      \
>   static __always_inline unsigned long kvm_##lname##_read(struct kvm_vcpu *vcpu)\
>   {									      \
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 79e5df5fbb32..1795702dc6de 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -4107,7 +4107,7 @@ void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
>   	vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
>   					  ~vcpu->arch.cr4_guest_rsvd_bits;
>   	if (!enable_ept)
> -		vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
> +		vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_TLB_BITS;
>   	if (is_guest_mode(&vmx->vcpu))
>   		vcpu->arch.cr4_guest_owned_bits &=
>   			~get_vmcs12(vcpu)->cr4_guest_host_mask;