Re: [PATCH] mtd: spi-nor: mt25qu: Ignore 6th ID byte

From: Michael Walle
Date: Tue Nov 23 2021 - 03:14:24 EST


Am 2021-11-23 08:45, schrieb Alexander Sverdlin:
On 22/11/2021 16:05, Michael Walle wrote:
Ignore 6th ID byte, secure version of mt25qu256a has 0x73 as 6th byte.

You don't have the non-security part by chance?

Unfortunately no. And this is exactly the trigger for this patch:
one can get "secure" parts from Micron even though these "features" are not

Mh, I'm undecided whether we should just duplicate the entry or if we
should ignore the last byte ("Device configuration information", where 00h
is standard). The commit which introduced the flash was 7f412111e276b.

Some people ask themselves why this table keeps growing if there is SFDP...
I see the point in fixups, but maybe at some point we will be able to support
some devices just out of the box?

Are these features detectable by SFDP? Without knowing anything, as you ignored
my former question, I'd say no. So there will be two flashes, one with these
features and one without, both presumably have the same SFDP. Thus we'd need
these two entries anyway if we ever support these features. I get that this
might be under NDA, but then talk to Micron; I for myself can't get a complete
picture here.

Can you elaborate on the 0x73? Is that a bitmask? If it was an enumeration,
I'd assumed it would be 01h (or some smaller value).

This "security addendum" where one need NDA just says "73h = Secure".
There is no explanation for it and no other variants.


I'd really suggest to try to autodetect whatever features are going to be
supported from this chip and only duplicate the entry if this auto-detection

There is a bigger patch series [1] from Tudor which you can try. You'd need to
respin your patch against that anyway.