Re: [PATCH] mtd: spi-nor: mt25qu: Ignore 6th ID byte
From: Alexander Sverdlin
Date: Tue Nov 23 2021 - 07:13:19 EST
On 22/11/2021 16:05, Michael Walle wrote:
> Thanks, so that's the SFDP data for the mt25qu256aba8e12-1sit part. and the
> jedec id is 20bb19104473, correct?
While we are at this part, I've encountered another issue:
The chip supports 1-1-1, 1-1-4 and 1-4-4 write OPs in extended SPI mode,
while only 1-1-0 erase. (as well as 4-4-4/4-4-0, but that's not the issue here,
Now the erase code (chip/sector) uses spi_nor_spimem_setup_op(nor, &op, nor->write_proto)
in both functions.
In my opinion, as I look into Micron or Macronix datasheets, write_proto has little to
do with erase_proto. (there is currently no separate erase_proto)
Before I come up with a totally wrong patch, wanted to ask your opinion, how should
it be solved, what do you think?
I do not see any erase-related tables for this in JESD216C.
I also cannot come up with an example of a chip with erase != 1-1-0.
Shall I hardcode 1-1-0 for erase?
Shall I introduce erase_proto? What would be the logic for its setting/discovery?