[irqchip: irq/irqchip-fixes] irqchip: nvic: Fix offset for Interrupt Priority Offsets

[irqchip-bot for Vladimir Murzin]

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     c5e0cbe2858d278a27d5b3fe31890aea5be064c4
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/c5e0cbe2858d278a27d5b3fe31890aea5be064c4
Author:        Vladimir Murzin <vladimir.murzin@xxxxxxx>
AuthorDate:    Wed, 01 Dec 2021 11:02:58 
Committer:     Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Thu, 02 Dec 2021 09:27:06 

irqchip: nvic: Fix offset for Interrupt Priority Offsets

According to ARM(v7M) ARM Interrupt Priority Offsets located at
0xE000E400-0xE000E5EC, while 0xE000E300-0xE000E33C covers read-only
Interrupt Active Bit Registers

Fixes: 292ec080491d ("irqchip: Add support for ARMv7-M NVIC")
Signed-off-by: Vladimir Murzin <vladimir.murzin@xxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20211201110259.84857-1-vladimir.murzin@xxxxxxx
---
 drivers/irqchip/irq-nvic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c
index 63bac3f..ba4759b 100644
--- a/drivers/irqchip/irq-nvic.c
+++ b/drivers/irqchip/irq-nvic.c
@@ -26,7 +26,7 @@
 
 #define NVIC_ISER		0x000
 #define NVIC_ICER		0x080
-#define NVIC_IPR		0x300
+#define NVIC_IPR		0x400
 
 #define NVIC_MAX_BANKS		16
 /*