[irqchip: irq/irqchip-fixes] irqchip/irq-gic-v3-its.c: Force synchronisation when issuing INVALL

[irqchip-bot for Wudi Wang]

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     d094b4332232c88d07d9884a9c32fec259984351
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/d094b4332232c88d07d9884a9c32fec259984351
Author:        Wudi Wang <wangwudi@xxxxxxxxxxxxx>
AuthorDate:    Wed, 08 Dec 2021 09:54:29 +08:00
Committer:     Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Wed, 08 Dec 2021 08:34:09 

irqchip/irq-gic-v3-its.c: Force synchronisation when issuing INVALL

INVALL CMD specifies that the ITS must ensure any caching associated with
the interrupt collection defined by ICID is consistent with the LPI
configuration tables held in memory for all Redistributors. SYNC is
required to ensure that INVALL is executed.

Currently, LPI configuration data may be inconsistent with that in the
memory within a short period of time after the INVALL command is executed.

Signed-off-by: Wudi Wang <wangwudi@xxxxxxxxxxxxx>
Signed-off-by: Shaokun Zhang <zhangshaokun@xxxxxxxxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Fixes: cc2d3216f53 ("irqchip: GICv3: ITS command queue")
Link: https://lore.kernel.org/r/20211208015429.5007-1-zhangshaokun@xxxxxxxxxxxxx
---
 drivers/irqchip/irq-gic-v3-its.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index eb0882d..0cb584d 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -742,7 +742,7 @@ static struct its_collection *its_build_invall_cmd(struct its_node *its,
 
 	its_fixup_cmd(cmd);
 
-	return NULL;
+	return desc->its_invall_cmd.col;
 }
 
 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,