RE: [PATCH v5 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver

[qinjian[覃健]]

> -----Original Message-----
> From: Marc Zyngier <maz@xxxxxxxxxx>
> Sent: Wednesday, December 8, 2021 3:45 PM
> To: qinjian[覃健] <qinjian@xxxxxxxxxxx>
> Cc: robh+dt@xxxxxxxxxx; mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; tglx@xxxxxxxxxxxxx; p.zabel@xxxxxxxxxxxxxx;
> linux@xxxxxxxxxxxxxxx; broonie@xxxxxxxxxx; arnd@xxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; Wells Lu 呂芳騰 <wells.lu@xxxxxxxxxxx>
> Subject: Re: [PATCH v5 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver
> 
> On 2021-12-08 07:15, qinjian[覃健] wrote:
> >> > +void sp_intc_set_ext(u32 hwirq, int ext_num)
> >> > +{
> >> > +	sp_intc_assign_bit(hwirq, REG_INTR_PRIORITY, !ext_num);
> >> > +}
> >> > +EXPORT_SYMBOL_GPL(sp_intc_set_ext);
> >>
> >> No way. We don't export random symbols without a good justification,
> >> and you didn't give any.
> >>
> >
> > This function called by SP7021 display driver to decide DISPLAY_IRQ
> > routing to which parent irq (EXT_INT0 or EXT_INT1).
> 
> Based on what? How can a display driver decide which parent is
> appropriate? What improvement does this bring?

In default, all IRQ routing to EXT_INT0, which processed by CPU0
Some device's IRQ need low latency, like display, so routing DISPLAY_IRQ to EXT_INT1,
which processed by CPU1 (set /proc/irq/<EXT_INT1>/smp_affinity_list)