Re: [PATCH v11 01/17] perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server

[Sean Christopherson]

On Fri, Dec 10, 2021, Like Xu wrote:
> From: Like Xu <like.xu@xxxxxxxxxxxxxxx>
> 
> From: Like Xu <like.xu@xxxxxxxxxxxxxxx>

Did one of these get handcoded?

> The new hardware facility supporting guest PEBS is only available on
> Intel Ice Lake Server platforms for now. KVM will check this field
> through perf_get_x86_pmu_capability() instead of hard coding the cpu
> models in the KVM code. If it is supported, the guest PEBS capability
> will be exposed to the guest.

So what exactly is this new feature?  I've speed read the cover letter and a few
changelogs and didn't find anything that actually explained when this feature does.

Based on the shortlog, I assume the feature handles translating linear addresses
via EPT?  If that's correct, then x86_pmu.pebs_vmx should be named something like
x86_pmu.pebs_ept.

That also raises the question of what will happen if EPT is disabled.  Presumably
things will Just Work since no additional translation is needed, but if that's the
case then arguably vmx_pebs_supported() should be:

	return boot_cpu_has(X86_FEATURE_PEBS) &&
	       (!tdp_enabled || kvm_pmu_cap.pebs_vmx);

I'm guessing no one actually cares about supporting PEBS on older CPUs using shadow
paging, but the changelog should at least call out that PEBS is allowed if and only
if "pebs_vmx" is supported for simplicity, even though it would actually work if EPT
is disabled.  And if for some reason it _doesn't_ work when EPT is disabled, then
vmx_pebs_supported() and friends need to actually check tdp_enabled.

Regardless, this changelog really, really needs an explanation of the feature.