Re: [PATCH 2/2] arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges

[Mark Rutland]

Hi Anshuman,

On Wed, Jan 12, 2022 at 03:04:59PM +0530, Anshuman Khandual wrote:
> Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
> well. Lets update these errata definition and detection to accommodate all
> new Cortex-X2 based cpu MIDR ranges.
> 
> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
> Cc: Will Deacon <will@xxxxxxxxxx>
> Cc: Mathieu Poirier <mathieu.poirier@xxxxxxxxxx>
> Cc: Suzuki Poulose <suzuki.poulose@xxxxxxx>
> Cc: coresight@xxxxxxxxxxxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
> ---
>  arch/arm64/Kconfig             | 12 ++++++------
>  arch/arm64/kernel/cpu_errata.c |  2 ++
>  2 files changed, 8 insertions(+), 6 deletions(-)

I think you've misssed Documentation/arm64/silicon-errata.rst -- for other
common errata we add lines for each affected part, e.g. as we do for
ARM64_ERRATUM_1418040.

Other than that, this looks good to me!

Thanks,
Mark.

> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index c4207cf9bb17..d8046c832225 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -671,14 +671,14 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
>  	bool
>  
>  config ARM64_ERRATUM_2119858
> -	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
> +	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
>  	default y
>  	depends on CORESIGHT_TRBE
>  	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
>  	help
> -	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.
> +	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
>  
> -	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
> +	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
>  	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
>  	  the event of a WRAP event.
>  
> @@ -761,14 +761,14 @@ config ARM64_ERRATUM_2253138
>  	  If unsure, say Y.
>  
>  config ARM64_ERRATUM_2224489
> -	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
> +	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
>  	depends on CORESIGHT_TRBE
>  	default y
>  	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
>  	help
> -	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.
> +	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
>  
> -	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved
> +	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
>  	  for TRBE. Under some conditions, the TRBE might generate a write to the next
>  	  virtually addressed page following the last page of the TRBE address space
>  	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 9e1c1aef9ebd..29cc062a4153 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
>  #endif
>  #ifdef CONFIG_ARM64_ERRATUM_2119858
>  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> +	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
>  #endif
>  	{},
>  };
> @@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = {
>  #endif
>  #ifdef CONFIG_ARM64_ERRATUM_2224489
>  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> +	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
>  #endif
>  	{},
>  };
> -- 
> 2.20.1
> 
> 
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