RE: [PATCH 03/23] clk: samsung: fsd: Add initial clock support

[Alim Akhtar]

>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@xxxxxxxxxxxxx]
>Sent: Thursday, January 13, 2022 6:20 PM
>To: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>; linux-arm-
>kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
>Cc: soc@xxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
>olof@xxxxxxxxx; linus.walleij@xxxxxxxxxx; catalin.marinas@xxxxxxx;
>robh+dt@xxxxxxxxxx; s.nawrocki@xxxxxxxxxxx; linux-samsung-
>soc@xxxxxxxxxxxxxxx; pankaj.dubey@xxxxxxxxxxx; linux-fsd@xxxxxxxxx;
>Jayati Sahu <jayati.sahu@xxxxxxxxxxx>; Ajay Kumar
><ajaykumar.rs@xxxxxxxxxxx>
>Subject: Re: [PATCH 03/23] clk: samsung: fsd: Add initial clock support
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> Add initial clock support for FSD (Full Self-Driving) SoC which is
>> required to bring-up platforms based on this SoC.
>>
>> Cc: linux-fsd@xxxxxxxxx
>> Signed-off-by: Jayati Sahu <jayati.sahu@xxxxxxxxxxx>
>> Signed-off-by: Ajay Kumar <ajaykumar.rs@xxxxxxxxxxx>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx>
>> Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
>> ---
>>  drivers/clk/samsung/Makefile  |   1 +
>>  drivers/clk/samsung/clk-fsd.c | 308
>++++++++++++++++++++++++++++++++++
>>  drivers/clk/samsung/clk-pll.c |   1 +
>>  drivers/clk/samsung/clk-pll.h |   1 +
>>  4 files changed, 311 insertions(+)
>>  create mode 100644 drivers/clk/samsung/clk-fsd.c
>>
>> diff --git a/drivers/clk/samsung/Makefile
>> b/drivers/clk/samsung/Makefile index c46cf11e4d0b..d66b2ede004c 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-
>exynos-audss.o
>>  obj-$(CONFIG_EXYNOS_CLKOUT)	+= clk-exynos-clkout.o
>>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7.o
>>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o
>> +obj-$(CONFIG_ARCH_TESLA_FSD)         += clk-fsd.o
>
>It should be rather it's own CONFIG_TESLA_FSD_CLK option, just like other
>Exynos designs. This keeps unified approach with existing Samsung clock
>Kconfig.
>
Ok, will add a separate config for this 

>>  obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
>> obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
>> obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o diff --git
>> a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c new
>> file mode 100644 index 000000000000..e47523106d9e
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-fsd.c
>> @@ -0,0 +1,308 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Common Clock Framework support for FSD SoC.
>> + *
>> + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
>> + *             https://www.samsung.com
>> + * Copyright (c) 2017-2022 Tesla, Inc.
>> + *             https://www.tesla.com
>> + *
>
>Drop the line break with empty * comment.
Will fix in next version
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/of.h>
>> +
>> +#include "clk.h"
>> +#include <dt-bindings/clock/fsd-clk.h>
>
>dt-bindings headers before local clk.h.
>
Noted, thanks
>> +
>> +/* Register Offset definitions for CMU_CMU (0x11c10000) */
>
>
>
>Best regards,
>Krzysztof