[PATCH v4 05/24] EDAC/amd64: Define function to denormalize address
From: Yazen Ghannam
Date: Thu Jan 27 2022 - 15:41:55 EST
Move the address denormalization into a separate helper function. This
will be further refactored in later patches.
Add the interleave address bit and the CS ID to the context struct.
These values will be used by multiple functions.
Signed-off-by: Yazen Ghannam <yazen.ghannam@xxxxxxx>
---
Link:
https://lore.kernel.org/r/20211028175728.121452-10-yazen.ghannam@xxxxxxx
v3->v4:
* Include pr_debug() on failure.
v2->v3:
* Was patch 10 in v2.
v1->v2:
* Moved from arch/x86 to EDAC.
drivers/edac/amd64_edac.c | 153 +++++++++++++++++++++-----------------
1 file changed, 84 insertions(+), 69 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 4e83a9be4724..9c61e3fa231a 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1075,6 +1075,8 @@ struct addr_ctx {
u16 nid;
u8 inst_id;
u8 map_num;
+ u8 intlv_addr_bit;
+ u8 cs_id;
bool hash_enabled;
};
@@ -1164,64 +1166,24 @@ static int get_dram_addr_map(struct addr_ctx *ctx)
return 0;
}
-static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
+static int denormalize_addr(struct addr_ctx *ctx)
{
- u64 dram_base_addr, dram_limit_addr, dram_hole_base;
-
u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
- u8 intlv_addr_sel, intlv_addr_bit;
- u8 num_intlv_bits, hashed_bit;
- u8 lgcy_mmio_hole_en;
- u8 cs_mask, cs_id = 0;
-
- struct addr_ctx ctx;
-
- if (!df_ops) {
- pr_debug("Data Fabric Operations not set");
- return -EINVAL;
- }
-
- memset(&ctx, 0, sizeof(ctx));
-
- /* Start from the normalized address */
- ctx.ret_addr = norm_addr;
-
- ctx.nid = nid;
- ctx.inst_id = umc;
-
- if (remove_dram_offset(&ctx)) {
- pr_debug("Failed to remove DRAM offset");
- goto out_err;
- }
-
- if (get_dram_addr_map(&ctx)) {
- pr_debug("Failed to get DRAM address map");
- goto out_err;
- }
-
- if (df_ops->get_intlv_mode(&ctx)) {
- pr_debug("Failed to get interleave mode");
- goto out_err;
- }
-
- lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1);
- intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF;
- intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7;
- dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16;
+ u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7;
+ u8 num_intlv_bits, cs_mask = 0;
/* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
if (intlv_addr_sel > 3) {
pr_err("%s: Invalid interleave address select %d.\n",
__func__, intlv_addr_sel);
- goto out_err;
+ return -EINVAL;
}
- intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1;
- intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3;
- dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
+ intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1;
+ intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3;
- intlv_addr_bit = intlv_addr_sel + 8;
+ ctx->intlv_addr_bit = intlv_addr_sel + 8;
/* Re-use intlv_num_chan by setting it equal to log2(#channels) */
switch (intlv_num_chan) {
@@ -1236,7 +1198,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
default:
pr_err("%s: Invalid number of interleaved channels %d.\n",
__func__, intlv_num_chan);
- goto out_err;
+ return -EINVAL;
}
num_intlv_bits = intlv_num_chan;
@@ -1244,7 +1206,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
if (intlv_num_dies > 2) {
pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
__func__, intlv_num_dies);
- goto out_err;
+ return -EINVAL;
}
num_intlv_bits += intlv_num_dies;
@@ -1256,7 +1218,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
if (num_intlv_bits > 4) {
pr_err("%s: Invalid interleave bits %d.\n",
__func__, num_intlv_bits);
- goto out_err;
+ return -EINVAL;
}
if (num_intlv_bits > 0) {
@@ -1269,41 +1231,43 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
* umc/channel# as instance id of the coherent slave
* for FICAA.
*/
- if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp))
- goto out_err;
+ if (df_indirect_read_instance(ctx->nid, 0, 0x50, ctx->inst_id, &ctx->tmp))
+ return -EINVAL;
- cs_fabric_id = (ctx.tmp >> 8) & 0xFF;
+ cs_fabric_id = (ctx->tmp >> 8) & 0xFF;
die_id_bit = 0;
/* If interleaved over more than 1 channel: */
if (intlv_num_chan) {
die_id_bit = intlv_num_chan;
cs_mask = (1 << die_id_bit) - 1;
- cs_id = cs_fabric_id & cs_mask;
+ ctx->cs_id = cs_fabric_id & cs_mask;
}
sock_id_bit = die_id_bit;
/* Read D18F1x208 (SystemFabricIdMask). */
if (intlv_num_dies || intlv_num_sockets)
- if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp))
- goto out_err;
+ if (df_indirect_read_broadcast(ctx->nid, 1, 0x208, &ctx->tmp))
+ return -EINVAL;
/* If interleaved over more than 1 die. */
if (intlv_num_dies) {
sock_id_bit = die_id_bit + intlv_num_dies;
- die_id_shift = (ctx.tmp >> 24) & 0xF;
- die_id_mask = (ctx.tmp >> 8) & 0xFF;
+ die_id_shift = (ctx->tmp >> 24) & 0xF;
+ die_id_mask = (ctx->tmp >> 8) & 0xFF;
- cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
+ ctx->cs_id |= ((cs_fabric_id & die_id_mask)
+ >> die_id_shift) << die_id_bit;
}
/* If interleaved over more than 1 socket. */
if (intlv_num_sockets) {
- socket_id_shift = (ctx.tmp >> 28) & 0xF;
- socket_id_mask = (ctx.tmp >> 16) & 0xFF;
+ socket_id_shift = (ctx->tmp >> 28) & 0xF;
+ socket_id_mask = (ctx->tmp >> 16) & 0xFF;
- cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
+ ctx->cs_id |= ((cs_fabric_id & socket_id_mask)
+ >> socket_id_shift) << sock_id_bit;
}
/*
@@ -1314,12 +1278,63 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
* bits there are. "intlv_addr_bit" tells us how many "Y" bits
* there are (where "I" starts).
*/
- temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0);
- temp_addr_i = (cs_id << intlv_addr_bit);
- temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
- ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
+ temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0);
+ temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit);
+ temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit))
+ << num_intlv_bits;
+ ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
}
+ return 0;
+}
+
+static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
+{
+ u64 dram_base_addr, dram_limit_addr, dram_hole_base;
+
+ u8 hashed_bit;
+ u8 lgcy_mmio_hole_en;
+
+ struct addr_ctx ctx;
+
+ if (!df_ops) {
+ pr_debug("Data Fabric Operations not set");
+ return -EINVAL;
+ }
+
+ memset(&ctx, 0, sizeof(ctx));
+
+ /* We start from the normalized address */
+ ctx.ret_addr = norm_addr;
+
+ ctx.nid = nid;
+ ctx.inst_id = umc;
+
+ if (remove_dram_offset(&ctx)) {
+ pr_debug("Failed to remove DRAM offset");
+ goto out_err;
+ }
+
+ if (get_dram_addr_map(&ctx)) {
+ pr_debug("Failed to get DRAM address map");
+ goto out_err;
+ }
+
+ if (df_ops->get_intlv_mode(&ctx)) {
+ pr_debug("Failed to get interleave mode");
+ goto out_err;
+ }
+
+ if (denormalize_addr(&ctx)) {
+ pr_debug("Failed to denormalize address");
+ goto out_err;
+ }
+
+ lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1);
+ dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16;
+
+ dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
+
/* Add dram base address */
ctx.ret_addr += dram_base_addr;
@@ -1339,12 +1354,12 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
(ctx.ret_addr >> 18) ^
(ctx.ret_addr >> 21) ^
(ctx.ret_addr >> 30) ^
- cs_id;
+ ctx.cs_id;
hashed_bit &= BIT(0);
- if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0)))
- ctx.ret_addr ^= BIT(intlv_addr_bit);
+ if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0)))
+ ctx.ret_addr ^= BIT(ctx.intlv_addr_bit);
}
/* Is calculated system address is above DRAM limit address? */
--
2.25.1