Re: [PATCH] Adding architectural support for HPE's GXP BMC. This is the first of a series of patches to support HPE's BMC with Linux Kernel.

[Krzysztof Kozlowski]

On 31/01/2022 19:52, Verdun, Jean-Marie wrote:
> Hi Krzysztof
> 
> We made some progress during the week-end and took the decision to breakdown the dts as you recommended (one dtsi for the SoC, and one dts per system board, we will start with the dl360 Gen10 server). We will send you some updates during the week, as I need to validate a few things with some of my colleagues regarding the partition tables definition which we kept (for the moment) into the ASIC definition, as all our implementation are using currently the same partition table.
> 
> We also removed many of the warning generated by the dtc compiler.
> 
> We will probably send the driver code at the same time than the dts update (or the next day). There will be a few of them including
> 
> - gpio
> - hwmon
> - udc / usb gadget
> - umac
> - i2c
> - watchdog
> - fbdev
> - kcs
> - vuart
> - spifi
> - clock
> 
> So as to simplify your understanding
> 
> - GXP is the name of the SoC. It has multiple implementations, which are currently compatibles. I don't think for the moment that we need to distinguished them. We might have a GXP v2 coming up but not before a certain amount of time which is far enough.
> - This SoC is used to implement BMC features of HPE servers (all ProLiant, many Apollo, and Superdome machines)
> 
> It does support many features including:
> - ARMv7 architecture, and it is based on a Cortex A9 core
> - Use an AXI bus to which 
> 	- a memory controller is attached, as well as multiple SPI interfaces to connect boot flash, and ROM flash, a 10/100/1000 Mac engine which supports SGMII (2 ports) and RMII
> 	- Multiple I2C engines to drive connectivity with a host infrastructure
> 	- A video engine which support VGA and DP, as well as an hardware video encder
> 	- Multiple PCIe ports
> 		- A PECI interface, and LPC eSPI
> 	- Multiple UART for debug purpose, and Virtual UART for host connectivity
> 	- A GPIO engine
> 
> Hope this help,
> 

Thanks, this helps, but it should be in the cover letter of the pathshet
plus some parts of it (subtract) in commit adding the new SoC support.


Best regards,
Krzysztof