[RFC PATCH 3/3] arm64: dts: s32g2: add USDHC support
From: Chester Lin
Date: Mon Feb 07 2022 - 08:50:42 EST
Add a mmc node to support USDHC on NXP S32G2 platforms.
Signed-off-by: Chester Lin <clin@xxxxxxxx>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 14 ++++++++++++++
arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 4 ++++
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 4 ++++
3 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 34652d36a9f1..fd073654d6f6 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/s32g2-clock.h>
/ {
compatible = "nxp,s32g2";
@@ -135,6 +136,19 @@ uart2: serial@402bc000 {
status = "disabled";
};
+ usdhc0: mmc@402f0000 {
+ compatible = "nxp,s32g2-usdhc";
+ reg = <0x402f0000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ clocks = <&scmi_clks S32G2_SCMI_CLK_USDHC_MODULE>,
+ <&scmi_clks S32G2_SCMI_CLK_USDHC_AHB>,
+ <&scmi_clks S32G2_SCMI_CLK_USDHC_CORE>;
+ clock-names = "ipg", "ahb", "per";
+ no-1-8-v;
+ status = "disabled";
+ };
+
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
reg = <0x50800000 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index 9118d8d2ee01..89428f1883d9 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -32,3 +32,7 @@ memory@80000000 {
&uart0 {
status = "okay";
};
+
+&usdhc0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index e05ee854cdf5..30eae51121de 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -38,3 +38,7 @@ &uart0 {
&uart1 {
status = "okay";
};
+
+&usdhc0 {
+ status = "okay";
+};
--
2.33.1