Re: [PATCH RESEND 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table

[Shawn Guo]

On Wed, Feb 09, 2022 at 11:32:58PM +0100, Yunus Bas wrote:
> The PHYTEC phyCORE-i.MX6QDL SOM-modules are operating with a slightly
> different voltage and frequency values in contrast to the generic
> i.MX6Q/DL tables. The values have been adjusted to achieve the most
> stable condition for the PHYTEC-modules. Introduce imx6q- and
> imx6dl-phycore dtsi files with the modified power tables.
> 
> Signed-off-by: Yunus Bas <y.bas@xxxxxxxxx>
> ---
>  .../boot/dts/imx6dl-phytec-mira-rdk-nand.dts  |  2 +-
>  .../boot/dts/imx6dl-phytec-phycore-som.dtsi   | 25 ++++++
>  .../boot/dts/imx6q-phytec-mira-rdk-emmc.dts   |  2 +-
>  .../boot/dts/imx6q-phytec-mira-rdk-nand.dts   |  2 +-
>  .../boot/dts/imx6q-phytec-phycore-som.dtsi    | 83 +++++++++++++++++++
>  5 files changed, 111 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi
>  create mode 100644 arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi
> 
> diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> index d906a7f05aaa..8ec27080ca1e 100644
> --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
> @@ -6,7 +6,7 @@
>  
>  /dts-v1/;
>  #include "imx6dl.dtsi"
> -#include "imx6qdl-phytec-phycore-som.dtsi"
> +#include "imx6dl-phytec-phycore-som.dtsi"
>  #include "imx6qdl-phytec-mira.dtsi"
>  #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
>  #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> diff --git a/arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi
> new file mode 100644
> index 000000000000..0985453b5ad6
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-phytec-phycore-som.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> + * Author: Yunus Bas <y.bas@xxxxxxxxx>
> + */
> +
> +#include "imx6qdl-phytec-phycore-som.dtsi"
> +
> +&cpu0 {
> +	operating-points = <
> +		/* kHz    uV */
> +		996000  1275000
> +		792000  1175000
> +		396000  1150000
> +	>;

Check Documentation/devicetree/bindings/opp/opp-v1.yaml to see how this
property should be coded properly.

Shawn

> +};
> +
> +&cpu1 {
> +	operating-points = <
> +		/* kHz    uV */
> +		996000  1275000
> +		792000  1175000
> +		396000  1150000
> +	>;
> +};
> diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> index 322f071d972f..7d947762f3b9 100644
> --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
> @@ -6,7 +6,7 @@
>  
>  /dts-v1/;
>  #include "imx6q.dtsi"
> -#include "imx6qdl-phytec-phycore-som.dtsi"
> +#include "imx6q-phytec-phycore-som.dtsi"
>  #include "imx6qdl-phytec-mira.dtsi"
>  #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
>  #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> index 3f13726c8058..afbb6681a6b5 100644
> --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
> @@ -6,7 +6,7 @@
>  
>  /dts-v1/;
>  #include "imx6q.dtsi"
> -#include "imx6qdl-phytec-phycore-som.dtsi"
> +#include "imx6q-phytec-phycore-som.dtsi"
>  #include "imx6qdl-phytec-mira.dtsi"
>  #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
>  #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
> diff --git a/arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi
> new file mode 100644
> index 000000000000..3ecb94379c8b
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-phytec-phycore-som.dtsi
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH
> + * Author: Yunus Bas <y.bas@xxxxxxxxx>
> + */
> +
> +#include "imx6qdl-phytec-phycore-som.dtsi"
> +
> +&cpu0 {
> +	operating-points = <
> +		/* KHz  uV */
> +		1200000 1300000
> +		996000  1250000
> +		852000  1250000
> +		792000  1175000
> +		396000  1075000
> +	>;
> +	fsl,soc-operating-points = <
> +		/* ARM kHz  SOC-PU uV */
> +		1200000 1275000
> +		996000	1250000
> +		852000	1250000
> +		792000	1250000
> +		396000	1250000
> +	>;
> +};
> +
> +&cpu1 {
> +	operating-points = <
> +		/* KHz  uV */
> +		1200000 1300000
> +		996000  1250000
> +		852000  1250000
> +		792000  1175000
> +		396000  1075000
> +	>;
> +	fsl,soc-operating-points = <
> +		/* ARM kHz  SOC-PU uV */
> +		1200000 1275000
> +		996000	1250000
> +		852000	1250000
> +		792000	1250000
> +		396000	1250000
> +	>;
> +};
> +
> +&cpu2 {
> +	operating-points = <
> +		/* KHz  uV */
> +		1200000 1300000
> +		996000  1250000
> +		852000  1250000
> +		792000  1175000
> +		396000  1075000
> +	>;
> +	fsl,soc-operating-points = <
> +		/* ARM kHz  SOC-PU uV */
> +		1200000 1275000
> +		996000	1250000
> +		852000	1250000
> +		792000	1250000
> +		396000	1250000
> +	>;
> +};
> +
> +&cpu3 {
> +	operating-points = <
> +		/* KHz  uV */
> +		1200000 1300000
> +		996000  1250000
> +		852000  1250000
> +		792000  1175000
> +		396000  1075000
> +	>;
> +	fsl,soc-operating-points = <
> +		/* ARM kHz  SOC-PU uV */
> +		1200000 1275000
> +		996000	1250000
> +		852000	1250000
> +		792000	1250000
> +		396000	1250000
> +	>;
> +};
> -- 
> 2.25.1
>