[PATCH v3 0/3] clk: qcom: Add display clock controller driver for SM6125

[Marijn Suijten]

Changes since v2:
- dt-bindings: Use a sensible `&dsi1_phy 1` example clock for the
  mandatory "dsi1_phy_pll_out_dsiclk", instead of a null phandle.

v2: https://lore.kernel.org/phone-devel/20220226200911.230030-1-marijn.suijten@xxxxxxxxxxxxxx/

Changes since v1:
- Documentation is dual-licensed;
- Documentation example now uses zero-clock for dsi1_phy pixel clock;
- SDX_GCC_65 is sorted in Kconfig/Makefile to easen adding this driver
  in the correct alphabetic spot;
- clk.h is replaced with clk-provider.h;
- ahb, mdp and rot source clocks use rcg2_shared_ops instead of standard
  ops;
- Unnecessary line breaks are removed when remaining under 80 chars.

v1: https://lore.kernel.org/linux-arm-msm/20211130212137.25303-1-martin.botka@xxxxxxxxxxxxxx/T/#u

Marijn Suijten (1):
  clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig

Martin Botka (2):
  dt-bindings: clock: add QCOM SM6125 display clock bindings
  clk: qcom: Add display clock controller driver for SM6125

 .../bindings/clock/qcom,dispcc-sm6125.yaml    |  87 +++
 drivers/clk/qcom/Kconfig                      |  21 +-
 drivers/clk/qcom/Makefile                     |   3 +-
 drivers/clk/qcom/dispcc-sm6125.c              | 709 ++++++++++++++++++
 .../dt-bindings/clock/qcom,dispcc-sm6125.h    |  41 +
 5 files changed, 854 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
 create mode 100644 drivers/clk/qcom/dispcc-sm6125.c
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm6125.h


base-commit: e6ada6df471f847da3b09b357e246c62335bc0bb
--
2.35.1