[esmil:visionfive 57/61] drivers/soc/sifive/sifive_l2_cache.c:158:3: error: implicit declaration of function 'writeq'
From: kernel test robot
Date: Tue Mar 08 2022 - 03:39:24 EST
Hi Emil,
First bad commit (maybe != root cause):
tree: https://github.com/esmil/linux visionfive
head: b75fcbba0e03fd9655bc4c8854422d51474664d3
commit: ad49c3fa8088809d886f993496240bd41155ab2a [57/61] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs
config: riscv-randconfig-r042-20220307 (https://download.01.org/0day-ci/archive/20220308/202203081628.ECRiVnPH-lkp@xxxxxxxxx/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project d271fc04d5b97b12e6b797c6067d3c96a8d7470e)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/esmil/linux/commit/ad49c3fa8088809d886f993496240bd41155ab2a
git remote add esmil https://github.com/esmil/linux
git fetch --no-tags esmil visionfive
git checkout ad49c3fa8088809d886f993496240bd41155ab2a
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/soc/sifive/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>
All error/warnings (new ones prefixed by >>):
>> drivers/soc/sifive/sifive_l2_cache.c:158:3: error: implicit declaration of function 'writeq' [-Werror,-Wimplicit-function-declaration]
writeq(line, l2_base + SIFIVE_L2_FLUSH64);
^
>> drivers/soc/sifive/sifive_l2_cache.c:148:19: warning: result of comparison of constant 36507222016 with expression of type 'unsigned long' is always false [-Wtautological-constant-out-of-range-compare]
(start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning and 1 error generated.
vim +/writeq +158 drivers/soc/sifive/sifive_l2_cache.c
a967a289f16969 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 126
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 127 #ifdef CONFIG_SIFIVE_L2_FLUSH
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 128 void sifive_l2_flush64_range(unsigned long start, unsigned long len)
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 129 {
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 130 unsigned long line;
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 131
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 132 if(!l2_base) {
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 133 pr_warn("L2CACHE: base addr invalid, skipping flush\n");
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 134 return;
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 135 }
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 136
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 137 /* TODO: if (len == 0), skipping flush or going on? */
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 138 if(!len) {
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 139 pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start);
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 140 return;
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 141 }
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 142
95728482b5e3e7 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 143 len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN);
95728482b5e3e7 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 144 start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN);
95728482b5e3e7 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 145
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 146 /* make sure the address is in the range */
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 147 if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 @148 (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 149 CONFIG_SIFIVE_L2_FLUSH_SIZE)) {
b2ba91ef9c8b60 drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21 150 WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 151 start, len);
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 152 return;
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 153 }
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 154
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 155 mb(); /* sync */
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 156 for (line = start; line < start + len;
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 157 line += SIFIVE_L2_FLUSH64_LINE_LEN) {
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 @158 writeq(line, l2_base + SIFIVE_L2_FLUSH64);
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 159 mb();
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 160 }
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 161 }
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 162 EXPORT_SYMBOL_GPL(sifive_l2_flush64_range);
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 #endif
def7ba448ac4b5 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 164
:::::: The code at line 158 was first introduced by commit
:::::: def7ba448ac4b53b788d238985ef97702dc802a1 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function
:::::: TO: Tom <support@xxxxxxxxx>
:::::: CC: Emil Renner Berthing <kernel@xxxxxxxx>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx