[irqchip: irq/irqchip-next] dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts

[irqchip-bot for Marc Zyngier]

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     dba07ad11384d6a4ece4acda1fbe726222ca7ad0
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/dba07ad11384d6a4ece4acda1fbe726222ca7ad0
Author:        Marc Zyngier <maz@xxxxxxxxxx>
AuthorDate:    Tue, 14 Dec 2021 16:49:04 
Committer:     Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Mon, 07 Feb 2022 16:00:42 

dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts

Some of the FIQ per-cpu pseudo-interrupts are better described with
a specific affinity, the most obvious candidate being the CPU PMUs.

Augment the AIC binding to be able to specify that affinity in the
interrupt controller node.

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
---
 Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
index c7577d4..85c85b6 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
@@ -70,6 +70,35 @@ properties:
   power-domains:
     maxItems: 1
 
+  affinities:
+    type: object
+    additionalProperties: false
+    description:
+      FIQ affinity can be expressed as a single "affinities" node,
+      containing a set of sub-nodes, one per FIQ with a non-default
+      affinity.
+    patternProperties:
+      "^.+-affinity$":
+        type: object
+        additionalProperties: false
+        properties:
+          apple,fiq-index:
+            description:
+              The interrupt number specified as a FIQ, and for which
+              the affinity is not the default.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 5
+
+          cpus:
+            $ref: /schemas/types.yaml#/definitions/phandle-array
+            description:
+              Should be a list of phandles to CPU nodes (as described in
+              Documentation/devicetree/bindings/arm/cpus.yaml).
+
+        required:
+          - fiq-index
+          - cpus
+
 required:
   - compatible
   - '#interrupt-cells'