Re: Asymmetric regmap read/write reg

[Mark Brown]

On Thu, Mar 10, 2022 at 01:54:08PM -0800, Colin Foster wrote:

> The Ocelot chip has requires 100ns between address write and when the
> address is ready to be clocked out. This can be dealt with in three
> different ways:
> 1. Use a slow enough clock speed
> 2. Use a delay between address write and value read
> 3. Clock out N padding bytes to account for the 100ns access time
> 
> Forcing a slow clock speed is obviously not ideal, and forcing a delay
> between "write_then_read" sounds too driver-specific, so option 3 seems
> like the best option - especially if bulk reads are utilized.
> 
> Where regmap comes in is specifically the padding bytes. Reads require

Why not implement this using a delay?  That seems both more
straightforward and likely tending to be more accurate given that clock
rates for SPI devices tend to be a bit vague.  Much less disruptive to
implement too.

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