Re: [PATCH 2/2] clk: zynq: Update the parameters to zynq_clk_register_periph_clk

[Stephen Boyd]

Quoting Shubhrajyoti Datta (2022-02-22 05:09:03)
> In case there are only one gate or the two_gate is 0 the clk1 clock
> passed is not used. We are passing 0 which is arm_pll.
> Pass a invalid clock instead.
> 
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx>
> ---

Applied to clk-next