RE: [PATCH] sched: topology: make cache topology separate from cpu topology
From: 王擎
Date: Sun Mar 13 2022 - 22:37:58 EST
> > From: Wang Qing <wangqing@xxxxxxxx>
> >
> > Some architectures(e.g. ARM64), caches are implemented below:
> > cluster: ****** cluster 0 ***** ****** cluster 1 *****
> > core: 0 1 2 3 4 5 6 7
> > cache(Leveln): **cache0** **cache1** **cache2** **cache3**
> > sd_llc_id(current): 0 0 0 0 4 4 4 4
> > sd_llc_id(should be): 0 0 2 2 4 4 6 6
> >
> > Caches and cpus have different topology, this causes cpus_share_cache()
> > return the wrong value, which will affect the CPU load balance.
> >
> > Cache topology should be separated with CPU topology, it can be obtained
> > from "next-level-cache" in DTS preferentially.
>
> If your clusters do not have cache, then you're currently setting
> SD_SHARE_PKG_RESOURCES wrong, if they do, things are correct.
If there is a shared cache(L3) between clusters(cls 0 and cls 1) for all cores,
but not within the cluster like above, should we set SD_SHARE_PKG_RESOURCES
for MC0(cls 0), or just set SD_SHARE_PKG_RESOURCES for CLS?
>
> If you want to represent L2, use the new fangled cluster level or
> something, that's what it's there for.
>
> That is, you can represent the above like:
>
> DIE: 0-7
> MC: 0-3, 4-7
> CLS: 0-1,1-2, 4-5,6-7
>
> But if there is cache at MC, LLC is what it is.
There is no CLS support for LTS now, any plans to backport?
Thanks,
Wang