[tip: timers/core] clocksource/drivers/exynos_mct: Bump up mct max irq number

[tip-bot2 for Alim Akhtar]

The following commit has been merged into the timers/core branch of tip:

Commit-ID:     f49b82a0a54fa85451ed96c35f24679522d59c7a
Gitweb:        https://git.kernel.org/tip/f49b82a0a54fa85451ed96c35f24679522d59c7a
Author:        Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
AuthorDate:    Mon, 21 Feb 2022 23:15:46 +05:30
Committer:     Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
CommitterDate: Mon, 07 Mar 2022 18:27:22 +01:00

clocksource/drivers/exynos_mct: Bump up mct max irq number

Bump-up maximum number of MCT IRQ to match the binding
documentation. This make driver scalable for SoC which
has more than 12 timer irqs, like recently added FSD SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
Link: https://lore.kernel.org/r/20220221174547.26176-2-alim.akhtar@xxxxxxxxxxx
Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
---
 drivers/clocksource/exynos_mct.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 341ee47..bcf2100 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -64,7 +64,8 @@
 #define MCT_G0_IRQ	0
 /* Local timers count starts after global timer count */
 #define MCT_L0_IRQ	4
-#define MCT_NR_IRQS	12
+/* Max number of IRQ as per DT binding document */
+#define MCT_NR_IRQS	20
 
 enum {
 	MCT_INT_SPI,