Re: [PATCH] clk: vc5: Enable VC5_HAS_PFD_FREQ_DBL on 5p49v6965

[Luca Ceresoli]

Hi Adam, Claude,

thanks for your patch.

On 13/03/22 12:57, Adam Ford wrote:
> The 5p49v6965 has a reference clock frequency doubler.
> Enabling it adds versaclock_som.dbl to the clock tree,
> but the output frequency remains correct.
>
> Suggested-by: Claude Fillion <Claude.Fillion@xxxxxxxxxxx>
> Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> 
> diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
> index e7be3e54b9be..4d190579e874 100644
> --- a/drivers/clk/clk-versaclock5.c
> +++ b/drivers/clk/clk-versaclock5.c
> @@ -1211,7 +1211,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = {
>  	.model = IDT_VC6_5P49V6965,
>  	.clk_fod_cnt = 4,
>  	.clk_out_cnt = 5,
> -	.flags = VC5_HAS_BYPASS_SYNC_BIT,
> +	.flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_PFD_FREQ_DBL,


If my understanding is correct, the doubler is not mentioned by the
datasheet, but it exists. Maybe it's worth a line of comment to help
future readers not waste their time in finding out:
  /* Frequency doubler not mentioned on datasheet */

Can you confirm that:
 - the en_ref_doubler bit value defaults to zero when reading it, as the
   register guide says?
 - if set to 1 the frequencies double?

With that confirmed, the patch looks good.

Thanks,
-- 
Luca