Re: [PATCH v2 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY

[Chen-Yu Tsai]

On Fri, Mar 18, 2022 at 9:56 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@xxxxxxxxxxxxx> wrote:
>
> Il 18/03/22 14:51, Krzysztof Kozlowski ha scritto:
> > On 18/03/2022 12:12, AngeloGioacchino Del Regno wrote:
> >> Il 18/03/22 10:54, Jianjun Wang ha scritto:
> >>> Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
> >>>
> >>> Signed-off-by: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>
> >>> ---
> >>>    .../bindings/phy/mediatek,pcie-phy.yaml       | 75 +++++++++++++++++++
> >>>    1 file changed, 75 insertions(+)
> >>>    create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> >>> new file mode 100644
> >>> index 000000000000..868bf976568b
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> >>> @@ -0,0 +1,75 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: MediaTek PCIe PHY
> >>> +
> >>> +maintainers:
> >>> +  - Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>
> >>> +
> >>> +description: |
> >>> +  The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    const: mediatek,mt8195-pcie-phy
> >>
> >> Since I don't expect this driver to be only for MT8195, but to be extended to
> >> support some more future MediaTek SoCs and, depending on the number of differences
> >> in the possible future Gen4 PHYs, even different gen's, I propose to add a generic
> >> compatible as const.
> >>
> >> So you'll have something like:
> >>
> >> - enum:
> >>       - mediatek,mt8195-pcie-phy
> >> - const: mediatek,pcie-gen3-phy
> >
> > I am not sure if this is a good idea. How sure are you that there will
> > be no different PCIe Gen3 PHY not compatible with this one?
> >
> >
>
> Thanks for pointing that out, I have underestimated this option.
>
> Perhaps Jianjun may be more informed about whether my proposal is valid or not.

Just FYI, for Allwinner and I believe Rockchip as well, the compatible strings
always list the first SoC the hardware block was seen on known at the time
of driver/binding submission. No generic compatible strings are ever used.

Not sure if that's the general rule or not.


ChenYu