[PATCH v4 16/16] dt-bindings: clock: fix some conversion clock issues for rockchip,rk3399-cru.yaml
From: Johan Jonker
Date: Sat Apr 02 2022 - 10:37:50 EST
With the YAML conversion somehow "assigned-xxx" properties where added.
If a proper clock is added to the cru node these properties are no longer
needed, so removed them.
With the conversion of rockchip,rk3399-cru.txt a table with external clocks
was copied. Include these clocks into the schema.
Add clocks and clocks-names to example and make them a requirement.
Reorder/restyle so that this file is line with the other Rockchip
CRU bindings.
Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx>
---
.../bindings/clock/rockchip,rk3399-cru.yaml | 55 ++++++++++---------
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
index e91147c84..4574727da 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
@@ -20,15 +20,8 @@ description: |
used in device tree sources. Similar macros exist for the reset sources in
these files.
There are several clocks that are generated outside the SoC. It is expected
- that they are defined using standard clock bindings with following
- clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "clkin_gmac" - external GMAC clock - optional,
- - "clkin_i2s" - external I2S clock - optional,
- - "pclkin_cif" - external ISP clock - optional,
- - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
- - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
properties:
compatible:
@@ -39,37 +32,41 @@ properties:
reg:
maxItems: 1
- "#clock-cells":
- const: 1
-
- "#reset-cells":
- const: 1
-
clocks:
minItems: 1
+ maxItems: 7
- assigned-clocks:
- minItems: 1
- maxItems: 64
-
- assigned-clock-parents:
+ clock-names:
minItems: 1
- maxItems: 64
-
- assigned-clock-rates:
- minItems: 1
- maxItems: 64
+ maxItems: 7
+ items:
+ enum:
+ - xin24m
+ - xin32k
+ - clkin_gmac
+ - clkin_i2s
+ - clk_usbphy0_480m
+ - clk_usbphy1_480m
+ - pclkin_cif
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
- description: >
- phandle to the syscon managing the "general register files". It is used
+ description:
+ Phandle to the syscon managing the "general register files". It is used
for GRF muxes, if missing any muxes present in the GRF will not be
available.
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
required:
- compatible
- reg
+ - clocks
+ - clock-names
- "#clock-cells"
- "#reset-cells"
@@ -80,6 +77,8 @@ examples:
pmucru: clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0xff750000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -87,6 +86,8 @@ examples:
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0xff760000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.20.1