[PATCH 5.16 0052/1017] clk: rockchip: re-add rational best approximation algorithm to the fractional divider

From: Greg Kroah-Hartman
Date: Tue Apr 05 2022 - 07:05:14 EST

From: Quentin Schulz <quentin.schulz@xxxxxxxxxxxxxxxxxxxxx>

commit 10b74af310735860510a533433b1d3ab2e05a138 upstream.

In commit 4e7cf74fa3b2 ("clk: fractional-divider: Export approximation
algorithm to the CCF users"), the code handling the rational best
approximation algorithm was replaced by a call to the core
clk_fractional_divider_general_approximation function which did the same
thing back then.

However, in commit 82f53f9ee577 ("clk: fractional-divider: Introduce
POWER_OF_TWO_PS flag"), this common code was made conditional on
CLK_FRAC_DIVIDER_POWER_OF_TWO_PS flag which was not added back to the
rockchip clock driver.

This broke the ltk050h3146w-a2 MIPI DSI display present on a PX30-based
downstream board.

Let's add the flag to the fractional divider flags so that the original
and intended behavior is brought back to the rockchip clock drivers.

Fixes: 82f53f9ee577 ("clk: fractional-divider: Introduce POWER_OF_TWO_PS flag")
Cc: stable@xxxxxxxxxxxxxxx
Cc: Quentin Schulz <foss+kernel@xxxxxxxxx>
Signed-off-by: Quentin Schulz <quentin.schulz@xxxxxxxxxxxxxxxxxxxxx>
Link: https://lore.kernel.org/r/20220131163224.708002-1-quentin.schulz@xxxxxxxxxxxxxxxxxxxxx
Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
drivers/clk/rockchip/clk.c | 3 +++
1 file changed, 3 insertions(+)

--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -180,6 +180,7 @@ static void rockchip_fractional_approxim
unsigned long rate, unsigned long *parent_rate,
unsigned long *m, unsigned long *n)
+ struct clk_fractional_divider *fd = to_clk_fd(hw);
unsigned long p_rate, p_parent_rate;
struct clk_hw *p_parent;

@@ -190,6 +191,8 @@ static void rockchip_fractional_approxim
*parent_rate = p_parent_rate;

clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);