Re: [PATCH] arch_topology: support parsing cache topology from DT

[Sudeep Holla]

On Wed, Apr 06, 2022 at 02:18:00AM -0700, Qing Wang wrote:
> From: wangqing <11112896@xxxxxxxxxx>
> 
> When ACPI is not enabled, we can parse cache topolopy from DT:
> *		cpu0: cpu@000 {
> *			next-level-cache = <&L2_1>;
> *			L2_1: l2-cache {
> * 				compatible = "cache";
> *				next-level-cache = <&L3_1>;
> * 			};
> *			L3_1: l3-cache {
> * 				compatible = "cache";
> * 			};
> *		};
> *
> *		cpu1: cpu@001 {
> *			next-level-cache = <&L2_1>;
> *		};
> *		cpu2: cpu@002 {
> *			L2_2: l2-cache {
> * 				compatible = "cache";
> *				next-level-cache = <&L3_1>;
> *			};
> *		};
> *
> *		cpu3: cpu@003 {
> *			next-level-cache = <&L2_2>;
> *		};
> cache_topology hold the pointer describing "next-level-cache", 
> it can describe the cache topology of every level.
> 
> Expand the use of llc_sibling when ACPI is not enabled.
>

You seem to have posted this patch as part of the series first. One patch
was rejected and then you post this without any history. It confuses if you
don't provide all the background/history.

Having said that, NACK for this patch as it stands. We have
drivers/base/cacheinfo.c which has all the parsing of cache information.
IIRC we already consider LLC but highlight if anything is particularly
missing. I am unable to follow/understand with you commit message. 

-- 
Regards,
Sudeep