Re: [PATCH] PCI: PM: Quirk bridge D3 on Elo i2

[Bjorn Helgaas]

On Mon, Apr 11, 2022 at 02:10:30PM +0200, Thorsten Leemhuis wrote:
> 
> 
> On 11.04.22 13:35, Rafael J. Wysocki wrote:
> > On Sun, Apr 10, 2022 at 11:16 AM Thorsten Leemhuis
> > <regressions@xxxxxxxxxxxxx> wrote:
> >>
> >> On 09.04.22 15:35, Rafael J. Wysocki wrote:
> >>> On Fri, Apr 8, 2022 at 9:53 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
> >>>>
> >>>> On Mon, Apr 04, 2022 at 04:46:14PM +0200, Rafael J. Wysocki wrote:
> >>>>> On Fri, Apr 1, 2022 at 1:34 PM Rafael J. Wysocki <rafael@xxxxxxxxxx> wrote:
> >>>>>> On Thu, Mar 31, 2022 at 11:57 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
> >>>>>>> On Thu, Mar 31, 2022 at 07:38:51PM +0200, Rafael J. Wysocki wrote:
> >>>>>>>> From: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
> >>>>>>>>
> >>>>>>>> If one of the PCIe root ports on Elo i2 is put into D3cold and then
> >>>>>>>> back into D0, the downstream device becomes permanently inaccessible,
> >>>>>>>> so add a bridge D3 DMI quirk for that system.
> >>>>>>>>
> >>>>>>>> This was exposed by commit 14858dcc3b35 ("PCI: Use
> >>>>>>>> pci_update_current_state() in pci_enable_device_flags()"), but before
> >>>>>>>> that commit the root port in question had never been put into D3cold
> >>>>>>>> for real due to a mismatch between its power state retrieved from the
> >>>>>>>> PCI_PM_CTRL register (which was accessible even though the platform
> >>>>>>>> firmware indicated that the port was in D3cold) and the state of an
> >>>>>>>> ACPI power resource involved in its power management.
> >>>>>>>> ...

> >>>> I don't understand all that's going on here, but I applied it to
> >>>> pci/pm for v5.19, thanks!
> >>> Thank you!
> >>
> >> Sorry, but this made me wonder: why v5.19? It's a regression exposed in
> >> v5.15, so it afaics would be good to get this in this cycle -- and also
> >> backported to v5.15.y, but it seem a tag to take care of that is
> >> missing. :-/

I moved it to for-linus for v5.18 and added a stable tag for v5.15+.