Re: [PATCH] mtd: spinand: add support for ESMT F50x1G41LB

[Chuanhong Guo]

On Wed, Apr 13, 2022 at 12:23 PM Chuanhong Guo <gch981213@xxxxxxxxx> wrote:
>
> This patch adds support for ESMT F50L1G41LB and F50D1G41LB.
> It seems that ESMT likes to use random JEDEC ID from other vendors.
> Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from
> Micron. For this reason, the ESMT entry is named esmt_c8 with explicit
> JEDEC ID in variable name.
>
> Datasheets:
> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf
> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf
>
> Signed-off-by: Chuanhong Guo <gch981213@xxxxxxxxx>
> [...]
> +static const struct spinand_info esmt_c8_spinand_table[] = {
> +       SPINAND_INFO("F50L1G41LB",
> +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f,
> +                               0x7f, 0x7f),

This patch is broken. SPI NAND core doesn't support 5-byte ID atm.

-- 
Regards,
Chuanhong Guo