[Patch v8 0/4] memory: tegra: Add MC channels and error logging

From: Ashish Mhetre
Date: Mon Apr 25 2022 - 03:52:51 EST

>From tegra186 onward, memory controllers support multiple channels.
Add memory controller channels in device tree and add support to map
address spaces of these channels in tegra MC driver.
When memory controller interrupt occurs, registers from these channels
are required to be read in order to get error information.
Add error logging support from tegra186 onward for memory controller

Ashish Mhetre (4):
memory: tegra: Add memory controller channels support
memory: tegra: Add MC error logging on tegra186 onward
dt-bindings: memory: tegra: Update validation for reg and reg-names
arm64: tegra: Add memory controller channels

Changes in v8:
- Updated the bindings patch commit message to reflect the ABI change
and added "tegra" in subject
- Updated function name with "mc_" prefix
- Used snprintf instead of sprintf
- Set mc->bcast_ch_regs to NULL in case of old bindings and checking for
NULL before accessing it

Changes in v7:
- Updated reg-names as per comments on v6
- Removed use of of_property_count_elems_of_size() and used broadcast
reg for checking whether old or new DTS is getting used
- Updated variable names as per comments on v6
- Added helper function for getting global_intstatus bit from channel
- Used to_platform_device() instead of passing pdev pointer to
- Allocated ch_regs at runtime
- Updated DT binding documentation to add validation for reg-names

Changes in v6:
- Added reg-names for each reg item of memory controller node
- Added logging for interrupts on multiple memory controller channels
- Added clearing interrupt support for global intstatus
- Updated DT binding documentation to work with existing DTS as well
- Updated function to get MC channels
- Updated variable names

Changes in v5:
- Updated patch sequence such that driver patches are before DT patches
- Fixed DT ABI break from v4
- Fixed smatch bug
- Updated description in DT binding documentation
- Updated variable names

Changes in v4:
- Added memory controller channels support
- Added newlines after every break statement of all switch cases
- Fixed compile error with W=1 build
- Fixed the interrupt mask bit logic

Changes in v3:
- Removed unnecessary ifdefs
- Grouped newly added MC registers with existing MC registers
- Removed unnecessary initialization of variables
- Updated code to use newly added field 'has_addr_hi_reg' instead of ifdefs

Changes in v2:
- Updated patch subject and commit message
- Removed separate irq handlers
- Updated tegra30_mc_handle_irq to be used for tegra186 onwards as well

.../nvidia,tegra186-mc.yaml | 80 +++++++++-
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 ++-
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 ++-
drivers/memory/tegra/mc.c | 140 ++++++++++++++++--
drivers/memory/tegra/mc.h | 43 +++++-
drivers/memory/tegra/tegra186.c | 43 ++++++
drivers/memory/tegra/tegra194.c | 9 ++
drivers/memory/tegra/tegra234.c | 8 +
include/soc/tegra/mc.h | 7 +
10 files changed, 356 insertions(+), 30 deletions(-)