[PATCH v1 01/11] perf mem: Add any cache level statistics for store operation

[Leo Yan]

Sometimes we don't know memory store operations happen on exactly which
cache level, so set the memory level flag PERF_MEM_LVLNUM_ANY_CACHE for
this case.  An usage case is that Arm SPE trace data sets this flag for
all the store operations due to we have no sufficient info for cache
level.

This patch is to add a new item "st_anylvl" in structure c2c_stats so
that support any cache level statistics for store operations.

Signed-off-by: Leo Yan <leo.yan@xxxxxxxxxx>
Tested-by: Ali Saidi <alisaidi@xxxxxxxxxx>
---
 tools/perf/util/mem-events.c | 4 ++++
 tools/perf/util/mem-events.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index db5225caaabe..bfbac365e1e4 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c
@@ -527,6 +527,7 @@ int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi)
 	u64 snoop  = data_src->mem_snoop;
 	u64 lock   = data_src->mem_lock;
 	u64 blk    = data_src->mem_blk;
+	u64 lvl_num = data_src->mem_lvl_num;
 	/*
 	 * Skylake might report unknown remote level via this
 	 * bit, consider it when evaluating remote HITMs.
@@ -621,6 +622,8 @@ do {				\
 		}
 		if (lvl & P(LVL, MISS))
 			if (lvl & P(LVL, L1)) stats->st_l1miss++;
+		if (lvl_num == P(LVLNUM, ANY_CACHE))
+			stats->st_anylvl++;
 	} else {
 		/* unparsable data_src? */
 		stats->noparse++;
@@ -647,6 +650,7 @@ void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add)
 	stats->st_noadrs	+= add->st_noadrs;
 	stats->st_l1hit		+= add->st_l1hit;
 	stats->st_l1miss	+= add->st_l1miss;
+	stats->st_anylvl	+= add->st_anylvl;
 	stats->load		+= add->load;
 	stats->ld_excl		+= add->ld_excl;
 	stats->ld_shared	+= add->ld_shared;
diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h
index 916242f8020a..e0e8057c52e8 100644
--- a/tools/perf/util/mem-events.h
+++ b/tools/perf/util/mem-events.h
@@ -63,6 +63,7 @@ struct c2c_stats {
 	u32	st_noadrs;           /* cacheable store with no address */
 	u32	st_l1hit;            /* count of stores that hit L1D */
 	u32	st_l1miss;           /* count of stores that miss L1D */
+	u32	st_anylvl;           /* count of stores with any cache level */
 	u32	load;                /* count of all loads in trace */
 	u32	ld_excl;             /* exclusive loads, rmt/lcl DRAM - snp none/miss */
 	u32	ld_shared;           /* shared loads, rmt/lcl DRAM - snp hit */
-- 
2.25.1