Add memory controller support for Nuvoton NPCM SoC.
Signed-off-by: Medad CChien <ctcchien@xxxxxxxxxxx>
Reviewed-by: Borislav Petkov <bp@xxxxxxxxx>
Reviewed-by: Paul Menzel <pmenzel@xxxxxxxxxxxxx>
Reported-by: kernel test robot <lkp@xxxxxxxxx>
error:
macro "edac_printk" requires 4 arguments, but only 2 given
warnings:
performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses]
mixing declarations and code is a C99 extension [-Wdeclaration-after-statement]
Note:
you can force an ecc event by writing a string to edac sysfs node
and remember to define CONFIG_EDAC_DEBUG to enable this feature
example: force a correctable event on checkcode bit 0
echo "CE checkcode 0" > /sys/devices/system/edac/mc/mc0/forced_ecc_error
---
drivers/edac/Kconfig | 9 +
drivers/edac/Makefile | 1 +
drivers/edac/npcm_edac.c | 680 +++++++++++++++++++++++++++++++++++++++
3 files changed, 690 insertions(+)
create mode 100644 drivers/edac/npcm_edac.c
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 58ab63642e72..64149b524f98 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -539,4 +539,13 @@ config EDAC_DMC520
Support for error detection and correction on the
SoCs with ARM DMC-520 DRAM controller.
+config EDAC_NPCM
+ tristate "Nuvoton NPCM DDR Memory Controller"
+ depends on (ARCH_NPCM || COMPILE_TEST)
+ help
+ Support for error detection and correction on the Nuvoton NPCM DDR
+ memory controller.
+ First, ECC must be configured in the BootBlock header. Then, this driver
+ will expose error counters via the EDAC kernel framework.
+
endif # EDAC
+module_platform_driver(npcm_edac_mc_driver);
+
+MODULE_AUTHOR("Medad CChien<ctcchien@xxxxxxxxxxx>");
+MODULE_DESCRIPTION("Nuvoton NPCM EDAC Driver");
+MODULE_LICENSE("GPL v2");