Re: [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers

[Jiaxun Yang]

在 2022/5/10 6:53, Haoran Jiang 写道:
> According to the loongson cpu manual,different cpu cores
> correspond to different interrupt status registers
NAK!

It is intentional to do so.

The per-core ISR register is broken on 3B1500. So we use general ISR 
register here.
The per-core variable is left for LS2K.

Thanks
- Jiaxun
> Signed-off-by: Haoran Jiang <jianghaoran@xxxxxxxxxx>
> ---
>   drivers/irqchip/irq-loongson-liointc.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 649c58391618..f4e015b50af0 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -195,7 +195,7 @@ static int __init liointc_of_init(struct device_node *node,
>   		}
>   
>   		for (i = 0; i < LIOINTC_NUM_CORES; i++)
> -			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> +			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
>   	}
>   
>   	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {