[PATCH 2/2] dt-bindings: misc: Add the system id binding for Altera(Intel) FPGA platform

[kah . jing . lee]

From: Kah Jing Lee <kah.jing.lee@xxxxxxxxx>

This binding is created for Altera(Intel) FPGA platform System ID soft IP.
The Altera(Intel) Sysid component is generally part of an FPGA design.
The component can be hotplugged when the FPGA is reconfigured.

Signed-off-by: Ley Foon Tan <lftan@xxxxxxxxxx>
Signed-off-by: Kah Jing Lee <kah.jing.lee@xxxxxxxxx>
---
 .../bindings/misc/intel,socfpga-sysid.yaml    | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml

diff --git a/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml b/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
new file mode 100644
index 000000000000..470444248365
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,socfpga-sysid.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Sysid IP core driver
+
+maintainers:
+  - Arnd Bergmann <arnd@xxxxxxxx>
+  - Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
+
+description: |
+  The Altera Sysid component is generally part of an FPGA design. The
+  component can be hotplugged when the FPGA is reconfigured.  This patch
+  fixes the driver to support the component being hotplugged.
+
+properties:
+  compatible:
+    items:
+      - const: intel,socfpga-sysid-1.0
+
+  reg:
+    items:
+      - description: physical address and length of the registers which
+          contain revision and debug features
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    sysid_qsys: sysid@10000 {
+        compatible = "intel,socfpga-sysid-1.0";
+        reg = < 0x10000 0x00000008 >;
+    };
-- 
2.25.1