Re: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port

[Bjorn Helgaas]

On Tue, Jun 21, 2022 at 05:06:51PM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
> 
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additonal register bit
>   to enable and handle legacy interrupts.
> 
> Changes in v5:
> - Added of_device_get_match_data to identify CPM version.
> 
> 
> Bharat Kumar Gogada (2):
>   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
>   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
> 
>  .../bindings/pci/xilinx-versal-cpm.yaml       | 48 ++++++++++++--
>  drivers/pci/controller/pcie-xilinx-cpm.c      | 62 ++++++++++++++++++-
>  2 files changed, 103 insertions(+), 7 deletions(-)

This is the third "v5" posting:

  #1 Jun 16 https://lore.kernel.org/r/20220616124429.12917-1-bharat.kumar.gogada@xxxxxxxxxx
  #2 Jun 18 https://lore.kernel.org/r/20220618024459.7554-1-bharat.kumar.gogada@xxxxxxxxxx
  #3 Jun 21 https://lore.kernel.org/r/20220621113653.2354462-1-bharat.kumar.gogada@xxxxxxxxxx

This makes things harder than necessary.

I commented on a couple things in #2, and you said you were going to
fix them, but they aren't fixed in #3.

It will also make things easier if you include the MAINTAINERS patch
in the same series.  There's no reason for it to be separate.

Can you please post a v6 with the updates?

Bjorn