So I actually tested and added logging to see if the CH_SAFE
register bits are set for the channel on the first iteration. From
what I could test (iperf3 with huge/non huge packets, TCP/UDP), it
always return true on the first try. So since I think Pavel solution
is ok to go with.
However, since ocelot_fdma_wait_chan_safe() is also called in the napi
poll function of this driver, I don't think sleeping is allowed (softirq
context) and thus I would suggest using the readx_poll_timeout_atomic()
function instead.
Regarding the delay to wait between each read, I don't have any
information about that possible value, the datasheet only says "wait
for the bit to be set" so I guess we'll have to live with an
approximate value.