Re: [PATCH] irqchip: or1k-pic: Undefine mask_ack for level triggered hardware

[Marc Zyngier]

On Tue, 28 Jun 2022 02:28:54 +0100,
Stafford Horne <shorne@xxxxxxxxx> wrote:
> 
> The mask_ack operation clears the interrupt by writing to the PICSR
> register.  This we don't want for level triggered interrupt because
> it does not actually clear the interrupt on the source hardware.
> 
> This was causing issues in qemu with multi core setups where
> interrupts would continue to fire even though they had been cleared in
> PICSR.
> 
> Just remove the mask_ack operation.
> 
> Signed-off-by: Stafford Horne <shorne@xxxxxxxxx>
> ---
> Note,
> 
> I currently have this queued with openrisc fixes for 5.19-rcX.  If this is ok
> with the IRQ maintainers I would like to have this merged via the OpenRISC
> queue.
> 
>  drivers/irqchip/irq-or1k-pic.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c
> index 49b47e787644..f289ccd95291 100644
> --- a/drivers/irqchip/irq-or1k-pic.c
> +++ b/drivers/irqchip/irq-or1k-pic.c
> @@ -66,7 +66,6 @@ static struct or1k_pic_dev or1k_pic_level = {
>  		.name = "or1k-PIC-level",
>  		.irq_unmask = or1k_pic_unmask,
>  		.irq_mask = or1k_pic_mask,
> -		.irq_mask_ack = or1k_pic_mask_ack,
>  	},
>  	.handle = handle_level_irq,
>  	.flags = IRQ_LEVEL | IRQ_NOPROBE,

Acked-by: Marc Zyngier <maz@xxxxxxxxxx>

Feel free to take this via your tree.

	M.

-- 
Without deviation from the norm, progress is not possible.