Re: [PATCH 4/4] riscv: implement cache-management errata for T-Head SoCs

[Samuel Holland]

On 6/19/22 3:32 PM, Heiko Stuebner wrote:
> The T-Head C906 and C910 implement a scheme for handling
> cache operations different from the generic Zicbom extension.
> 
> Add an errata for it next to the generic dma coherency ops.
> 
> Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>

Thanks for the update!

Reviewed-by: Samuel Holland <samuel@xxxxxxxxxxxx>
Tested-by: Samuel Holland <samuel@xxxxxxxxxxxx>