[PATCH v1 0/2] Add the JH7100's Monitor Core

From: Conor Dooley
Date: Mon Jul 11 2022 - 14:44:17 EST

From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

Hey Emil,

Following on from my RFC [0], here's the real patches adding the
monitor core for the JH7100 w/ the ordering changed as requested.

I had a look in the SiFive E24 docs [1] & in [2] which said "16KB
I-cache with 32 Byte cache line". Didn't have anything else to go on,
so I kept the same ratio between lines/sets/size as other SiFive
monitor cores, but since they're not 32 bit I dunno if that's correct
(IOW it is a wild guess).

The dts patch depends on adding the series adding the cpu-map [3]:


0: https://lore.kernel.org/linux-riscv/20220710111330.3920699-1-mail@xxxxxxxxxxx/
1: https://sifive.cdn.prismic.io/sifive/dc408861-94ce-4d82-a704-caddec98609d_e24_core_complex_manual_21G3.pdf
2: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
3: https://lore.kernel.org/linux-riscv/20220705190435.1790466-1-mail@xxxxxxxxxxx/

Conor Dooley (2):
dt-bindings: riscv: document the sifive e24
riscv: dts: starfive: add the missing monitor core

.../devicetree/bindings/riscv/cpus.yaml | 2 ++
arch/riscv/boot/dts/starfive/jh7100.dtsi | 21 +++++++++++++++++++
2 files changed, 23 insertions(+)

base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563
prerequisite-patch-id: 946df827e9dad8ca6e9751fe4ba01fd5fe9d18cc
prerequisite-patch-id: 59626290ee7b1e725bd446a4b7170ee2d6ca9bc0
prerequisite-patch-id: e57a94cb7d69855a4e2d6044dcf86fbfe35cb696
prerequisite-patch-id: 0ba94fd09377953ec4e9692358de569a7932bfa3
prerequisite-patch-id: 398e9b178ce51c924bbd9115020d84b677f773bb