[PATCH 1/2] dt-bindings: mailbox : marvell,mbox: Add bindings

[Wojciech Bartczak]

This patch adds device tree binding for Marvell Message Handling Unit
(MHU) controller.

Signed-off-by: Wojciech Bartczak <wbartczak@xxxxxxxxxxx>
---
 .../mailbox/marvell,mbox-mailbox.yaml         | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mailbox/marvell,mbox-mailbox.yaml

diff --git a/Documentation/devicetree/bindings/mailbox/marvell,mbox-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/marvell,mbox-mailbox.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d9a6e14dcb12da6c3a9db2dfafc075ccefa8711c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/marvell,mbox-mailbox.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/marvell,mbox-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Message Handling Unit
+
+maintainers:
+  - Wojciech Bartczak <wbartczak@xxxxxxxxxxx>
+  - Piyush Malgujar <pmalgujar@xxxxxxxxxxx>
+
+description:
+  The Marvell's Message Handling Unit is a mailbox controller
+  with a single channel used to communicate with System Control Processor.
+  Driver supports series of cn9x and cn10x SoC.
+  Sole purpose of the link is to exchange SCMI related data with SCP.
+  The link has hardwired configuration, it uses simple notification scheme
+  over shared memory block to push data back and forth.
+  Interrupts used by mailbox may be configured in two ways,
+  as SPI interrupts, then driver uses platform device forntend.
+  Other way is to use PCI bus frontend with LPI interrupts.
+
+properties:
+  compatible:
+    items:
+      - const: marvell,mbox
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: interrupt type
+        const: 0
+      - description: interrupt number
+      - description: interrupt trigger type
+        const: 1
+
+  '#mbox-cells':
+    description: Index of the channel
+    const: 1
+
+  shmem:
+    description:
+      List of phandle pointing to the shared memory area between SCP and AP.
+      The area is used to exchange additional information not covered by SCMI.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - '#mbox-cells'
+  - shmem
+
+additionalProperties: false
+
+examples:
+  - |
+    soc@0 {
+      reg = <0 0>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+      sram@36,0 {
+        compatible = "cpc-shmem";
+        reg = <0x86d0 0xdd400 0 0x200>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0x0 0x86d0 0xdd400 0x200>;
+
+        scp_to_cpu0: scp-shmame@0 {
+          compatible = "cpc-shmem";
+          reg = <0x0 0x0 0x200>;
+        };
+      };
+
+      mailbox0: mailbox@28,0 {
+        #mbox-cells = <1>;
+        compatible = "marvell,mbox";
+        reg = <0xe000 0 0 0>;
+        shmem = <&scp_to_cpu0>;
+      };
+    };
+  - |
+    soc@1 {
+      reg = <1 0>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+      sram@36,0 {
+        compatible = "cpc-shmem";
+        reg = <0x86d0 0xdd400 0 0x200>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0x0 0x86d0 0xdd400 0x200>;
+
+        scp_to_cpu1: scp-shmame@1 {
+          compatible = "cpc-shmem";
+          reg = <0x0 0x0 0x200>;
+        };
+      };
+
+      mailbox1: mailbox@82c000000000 {
+        #mbox-cells = <1>;
+        compatible = "marvell,mbox";
+        reg = <0x82c0 0x00000000 0x0 0x100000>;
+        interrupt-parent = <&gic0>;
+        interrupts = <0 59 1>;
+        shmem = <&scp_to_cpu1>;
+      };
+    };
-- 
2.17.1